Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package and its manufacturing method. The manufacturing method is to first provide a carrier with a semiconductor element, and then form a packaging layer with at least one opening on the carrier, so that the packaging layer covers the semiconductor element. , and the side of the opening is a smooth surface; then, a circuit layer is formed on the second surface of the encapsulation layer, and the circuit layer has a conductor formed in the opening, and then the carrier is removed, so that by simultaneously Making the encapsulation layer and the opening can not only prevent the wall surface of the opening from being too rough, but also greatly shorten the process time.

Description

technical field [0001] The invention relates to a packaging process, in particular to a semiconductor package capable of avoiding the problem of laser drilling and its manufacturing method. Background technique [0002] With the evolution of semiconductor packaging technology, different packaging types have been developed for semiconductor devices. In order to improve electrical functions and save packaging space, different three-dimensional packaging technologies have been developed, such as fan-out packaging stacks. Stacking (Fan Out Package on package, FO PoP for short), etc., to cope with the greatly increased number of input / output ports on various chips, and then integrate integrated circuits with different functions into a single package structure. The heterogeneous integration feature of package (SiP) can integrate electronic components with different functions, such as memory, central processing unit, graphics processor, image application processor, etc., through st...

AI Technical Summary

Problems solved by technology

[0010] However, in the existing manufacturing method of the semiconductor package 1, since a plurality of openings 130 are formed by laser, the thermal effect of the laser will cause the wall surface of the opening 130 to be extremely rough (such as Figure 1C As shown in the rough surface 130a), so that when the conductive column 14 is produced by electroplating, the electroplating quality is not good, thus causing problems such as low yield rate and poor product reliability.

[0011] In addition, although the opening 130 can be formed by etching to avoid the occurrence of the rough surface 130a, if the opening 130 with a diameter of more than 100um is to be formed, the process time of the etching method is too long, and thus the cost will be greatly increased.

[0012] In addition, the thermal release layer 110 is flexible, and its coefficient of thermal expansion (Coefficient of thermal expansion, CTE) and the lateral thrust generated by the colloid flow when the encapsulation layer 13 is injected into the encapsulation mold will affect the semiconductor element together. 10 fixed accuracy, that is, it is easy to cause the semiconductor element 10 to be offset, so that the semiconductor element 10 is not placed on the predetermined position of the thermalization release layer

Therefore, the alignment between the wiring redistribution layer 15 and the electrode pad 100 of the semiconductor element 10 will be offset, and when the size of the carrier 11 is larger, the positional tolerance between each of the semiconductor elements 10 will be increased accordingly. If the offset tolerance is too large, the wiring redistribution layer 15 cannot be connected to the electrode pad 100, that is, the electrical connection between the wiring redistribution layer 15 and the semiconductor element 10 will be greatly affected. , resulting in problems such as low yield rate and poor product reliability

Images