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ROM memory cell, storage array, memory and reading method

A technology of storage unit and storage array, which is applied in the fields of memory and readout, storage array, and ROM storage unit, can solve the problems of inability to further reduce the memory chip area and low storage density, and achieve easy implementation, increase storage density, and circuit simple effect

Active Publication Date: 2016-02-17
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, the above-mentioned ROM storage units of the current technology can only store one bit of storage information, and the storage density is very low, which cannot further reduce the chip area of ​​the memory.

Method used

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  • ROM memory cell, storage array, memory and reading method
  • ROM memory cell, storage array, memory and reading method
  • ROM memory cell, storage array, memory and reading method

Examples

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Embodiment Construction

[0057] In order to make the purpose, features and effects of the present invention more obvious and understandable, the specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0058] Many specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways than described here, so the present invention is not limited by the specific embodiments disclosed below.

[0059] With reference to the ROM storage unit in the prior art, its constituent unit is a MOS transistor, and the channel control capability of this MOS transistor is single, therefore, as figure 2 or image 3 The memory cells shown, whether word line programming or bit line programming, can only store logic states by turning on and off MOS transistors, so the amount of information stored per unit is limited, and the chip...

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PUM

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Abstract

The invention relates to a ROM memory cell, a storage array, a memory and a reading method. The ROM memory cell is at least formed by a CG-FinFET transistor and / or an IG-FinFET transistor. According to the invention, information storage density of the ROM memory cell can be increased.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a ROM storage unit, a storage array, a memory and a reading method. Background technique [0002] In integrated circuit design, for memory, it is the trend to increase storage density, reduce unit information storage cost, and reduce chip area. Under process conditions such as 40nm and below, due to the limitation of process rules, the area of ​​ROM storage unit cannot be reduced proportionally with the process size, and the storage area of ​​unit information is not satisfactory. [0003] The transistors in a traditional ROM memory cell share a source and the source is commonly connected to the ground voltage VSS, such as figure 1 What is shown is a schematic diagram of the circuit structure of a traditional ROM storage unit. It includes: NMOS transistor MOS11, and NMOS transistor MOS12. The sources of these two NMOS transistors are connected to the ground voltage VSS, the drains of th...

Claims

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Application Information

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IPC IPC(8): G11C17/12
Inventor 王林
Owner SPREADTRUM COMM (SHANGHAI) CO LTD
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