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Fin field effect transistor and method of forming the same

A fin field effect and transistor technology, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of unstable electrical performance of FinFET and affecting the performance of FinFET.

Active Publication Date: 2018-08-10
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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Problems solved by technology

[0008] However, with the continuous development of Fin FETs, it is found that the electrical properties of Fin FETs formed by existing processes are unstable, which affects the performance of Fin FETs. Therefore, how to improve the performance of Fin FETs is an urgent problem for those skilled in the art.

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  • Fin field effect transistor and method of forming the same
  • Fin field effect transistor and method of forming the same
  • Fin field effect transistor and method of forming the same

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Embodiment Construction

[0062] As mentioned in the background technology, the electrical performance stability of the fin field effect transistor formed by the existing process is poor. In order to obtain the reasons for the poor electrical performance stability, the fin field effect transistor in the working state is analyzed : After a voltage is applied to the gate of the FinFET, a large amount of fixed charge (fixed oxide charge) will accumulate at the junction of the fin and the oxide layer.

[0063] refer to image 3 and Figure 4 , respectively show the electrical performance test diagrams of fins and junctions with oxide layers in conventional NMOS transistors and PMOS transistors. Among them, the vertical axis is the threshold voltage, the horizontal axis is the amount of fixed charge, L1 and L3 are the electrical performance curves of fins with a width of about 6 nm, and L2 and L4 are the electrical performance curves of fins with a width of about 9 nm. Compared Figure 4 and image 3 It...

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Abstract

The invention provides a fin type field effect transistor and a formation method thereof. The formation method of a fin type field effect transistor comprises: ions are implanted into a semiconductor substrate, a first region doped with ions is formed in the semiconductor substrate, and the rest region of the semiconductor substrate serves as a second region; the first region and the second region are etched to form a fin, wherein the etching rate of the first region is lower than the etching rate of the second region, and thus the fin contains an ion implantation layer formed by etching the first region, wherein the width of the ion implantation layer is larger than that of the fin above the ion implantation layer; and a dielectric layer is formed on the semiconductor substrate and is exposed out of the ion implantation layer, a grid electrode crossing the fin is formed, and a source-drain region is formed in the fin. With the ion implantation layer, source-drain ion diffusion that is caused by source-drain ion implantation into the fin can be effectively inhibited, so that the depth of the ions in the source-drain region can be reduced, the accumulated fixed charge quantity at the juncture of the fin and the dielectric layer can be reduced during the application process, and thus the electrical performance of the fin type field effect transistor can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor formation, in particular to a fin field effect transistor and a forming method thereof. Background technique [0002] With the rapid development of integrated circuit (abbreviated as IC) manufacturing technology, the process nodes of traditional integrated circuits are gradually reduced, the size of integrated circuit devices is continuously reduced, and the manufacturing process of integrated circuit devices is constantly innovated to improve the performance of integrated circuit devices. [0003] For example, in MOS transistors, the ideal threshold voltage is obtained by forming metals with different work functions between the high-K dielectric layer and the metal gate, thereby improving device performance. However, with the gradual reduction of feature size, traditional planar MOS transistors can no longer meet the requirements for device performance. For example, the control ability of planar MOS ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 张海洋张璇
Owner SEMICON MFG INT (SHANGHAI) CORP