DP video signal timing sequence recovery device and method

Abstract

The invention relates to the technical field of a DP video signal and specifically relates to a DP video signal timing sequence recovery device and method. The DP video signal timing sequence recovery device comprises a DP decoding module, a video timing sequence generation module, a double-clock first-in first-out module, a control module and a phase-locked loop module. The method is characterized by carrying out DP decoding to generate MSA parameters, a first video pixel, a link clock and a link rate; storing the first video pixel obtained through DP decoding according to the link clock; configuring phase-locked loop frequency dividing ratio according to the MSA parameters and the link rate obtained through DP decoding, and generating a pixel clock according to the frequency dividing ratio; generating a horizontal synchronizing signal VS, a field synchronizing signal HS, and an effective display data gating signal DE according to the pixel clock and based on the MSA parameters obtained through DP decoding; and serving the horizontal synchronizing signal VS, the field synchronizing signal HS and the effective display data gating signal DE as a data reading control signal of the double-clock first-in first-out module, reading the first video pixel according to the pixel clock and generating a second video pixel and output the second video pixel. Conversion of the DP signals into other video signals can be realized only through an FPGA, so that DDR external storage device and power supply part thereof are saved, and PCB layout difficulty is small and system stability is higher.

Description

technical field [0001] The present invention relates to the technical field of DP video signals, in particular to a timing recovery device and method for DP video signals. Background technique [0002] As a high-bandwidth digital display interface, DP (DisplayPort) can support high resolution and high frame rate, and is often used as an input interface for video sources in the field of module testing. However, because the DP interface is based on the particularity of the micro-packet structure, in order to realize the precise realization of PatternTiming in the traditional video interface conversion, the transfer scheme based on the DDR external memory (DoubleDataRate double-rate synchronous dynamic random access memory) buffer is usually adopted. The PCB design layout and routing between the FPGA and the DDR external memory are difficult, and the signal quality is easily interfered by other signals; at the same time, the FPGA is complicated to read and write DDR data, and t...

AI Technical Summary

Problems solved by technology

PCB design layout and routing between FPGA and DDR external memory is difficult, and the signal quality is easily interfered by other signals; at the same time, FPGA reads and writes DDR data complicatedly, the entire circuit cost is high, and maintenance is difficult

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