Decoding circuit for POWER instruction set vector coprocessor

A technology of coprocessor and decoding circuit, which is applied in the field of decoding circuit, can solve the problems of waste of resources and power consumption, and achieve the effects of reducing hardware overhead, improving stability, and simple judgment logic

Inactive Publication Date: 2016-03-23
TIANJIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The entire decoding process is equivalent to a process of encoding first and then decoding, resulting in a waste of resources and an increase in power consumption

Method used

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  • Decoding circuit for POWER instruction set vector coprocessor

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Embodiment Construction

[0025] The decoding circuit of a POWER instruction set vector coprocessor of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0026] Such as figure 1 As shown, a decoding circuit of the POWER instruction set vector coprocessor of the present invention includes a first determiner 110, a first setter 120, a second determiner 130, and a second setter 140 that are connected in sequence, wherein ,

[0027] The input terminal of the first determiner 110 is connected to the output terminal of the main processor 200, and is used to receive an instruction from the main processor 200, determine whether the instruction is a valid vector coprocessor instruction, and send the determination result To the first setter 120;

[0028] The output of the first setter 120 is also connected to the input terminal of the main processor 200 for feeding back to the main processor 200 whether the instruction issued by the main processor 200 is a ...

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Abstract

The invention relates to a decoding circuit for a POWER instruction set vector coprocessor. The input end of a first judger is connected to the output end of a main processor and used for receiving an instruction and judging whether the instruction is an effective instruction or not; the output of a first setter is connected to the input end of the main processor and used for feeding back the fact that the instruction is effective or ineffective to the main processor, enabling the effective marking position of the instruction of the vector coprocessor to be high when the effective instruction information of the first judger is received, otherwise, enabling the effective marking position of the instruction of the vector coprocessor to be low, and sending to a second judger; the input end of the second judger is connected to the output end of the main processor; after the effective information of the first setter is received, the data source of operation data required for a function execution unit and a functional unit, which the instruction belongs to, is judged and sent into a second setter; and the second setter sends a control signal corresponding to a judging result of the second judger and the operation data to be read by the instruction to different function execution units. According to the invention, the required judging logic is simpler when the functional unit identifies the specific instruction type of the received instruction.

Description

Technical field [0001] The invention relates to a decoding circuit. In particular, it relates to a decoding circuit of a POWER instruction set vector coprocessor. Background technique [0002] SIMD (SingleInstructionMultipleData) is a data-level parallel technology that performs the same operation on multiple data. The key to SIMD technology is to perform multiple operations in a single instruction at the same time to increase the throughput of the processor. This feature makes SIMD technology particularly suitable for data-intensive operations such as multimedia applications. Now mainstream processors have their SIMD instruction subsets, such as X86's MMX or SSE, ARM's NEON instruction subset, and PowerPC's Altivec instruction subset. In modern multi-core processors, each core on the processor is usually equipped with a dedicated SIMD coprocessor, also known as VectorCoprocessor (VP). As a key part of the overall performance of the coprocessor, the primary decoding circuit of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/38G06F15/80
CPCG06F9/30036G06F9/3887G06F15/8007
Inventor 郭炜王捷魏继增
Owner TIANJIN UNIV
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