Automatic endurance test device and test method of discrete memory

Abstract

The invention relates to an automatic endurance test device and test method of a discrete memory. The test device comprises a general control board and a driving board, wherein the general control board controls the driving board to carry out an endurance test on a chip to be tested; the general control board comprises a power supply unit, a general control unit, a master control unit, a clock unit, a reset unit and communication contact pin modules; the driving board comprises a communication control unit, a test unit and a fixed connection hole; in the communication control unit, a signal branching module is used for amplifying the received signal of the driving board and independently sending the received signal to each chip to be tested; a dial-up control module is used for selecting test voltage and switches; and the communication pin modules are independently installed on the general control board and the driving board for transmitting the signal of the driving board to the driving board. The test device and the test method of the automatic endurance test device can finish a cyclic assessment test of endurance on a chip memory without using an automatic tester or a computer / card reader, and have the characteristics of cost saving and high efficiency.

Description

technical field [0001] The invention relates to the fields of integrated circuit memory testing and memory reliability assessment, in particular to a discrete integrated circuit chip automatic endurance testing device and a testing method thereof. Background technique [0002] With the continuous increase of integrated circuit integration, the continuous expansion of integrated circuit application fields, and the more diversified integrated circuit functions, the reliability test of integrated circuit chips has been paid more and more attention. Technology update and cost are also getting more and more attention; integrated circuit endurance assessment is to assess the total number of erases and writes that can be realized by the memory, and is one of the most important indicators for the reliability assessment of integrated circuit memory, so the endurance assessment test of memory is the Required assessment items and routine inspection items for granular products and SOC p...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, the endurance reliability test of integrated circuits mostly adopts the following methods: the wafer-level endurance reliability test adopts the probe sticking needle, and the endurance test is carried out by using the automatic tester to perform the endurance test by cyclically erasing the memory through the test interface, while The finished memory particles and SOC products basically use computers, card readers and other equipment to perform memory endurance and reliability assessment tests or routine inspection tests; this method requires automatic testers or computer / readers. The card device sends the erase command to the control end of the memory particle or the CPU end of the SOC, and then the control end or the CPU performs cyclic erase and write on the memory area. It can be seen from the process that the sending and receiving process of the command will consume most of the time. Test time, making endurance tests less efficient

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