Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a substrate and a lamination. The substrate has a first area, a second area and a third area, wherein the third area is configured between the first area and the second area. As the top surface of the substrate in the first area is lower than the top surface of the substrate in the second area, the substrate in the third area has a first step height. The lamination is configured on the substrate in the first and third areas. The top surface of the lamination in the first and third areas and the top surface of the substrate in the second area are substantially coplanar.

Description

technical field [0001] The present invention relates to an electronic component and its manufacturing method, and in particular to a semiconductor component and its manufacturing method. Background technique [0002] With the rapid development of technology, in order to reduce costs, simplify process steps and save chip area, it has gradually become a trend to integrate components in the memory cell array area and the peripheral circuit area on the same chip. However, there is a rather large step height (StepHeight) in the boundary region between the memory cell array region and the peripheral circuit region, which increases the complexity of subsequent processes. [0003] figure 1 It is a schematic cross-sectional view of a known semiconductor device. Please refer to figure 1 For example, in a known semiconductor device, in order to reduce the height of the stack 12 on the surface of the substrate 10 , a part of the substrate 10 in the memory cell array region 110 is fir...

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Problems solved by technology

However, since the etching rates of the silicon nitride layer 14 and the silicon oxide layer 16 are different, after the excess silicon nitride layer 14 and the silicon oxide layer 16 are removed by a wet etching process, the silicon nitride layer 14 Recesses 20 are likely to be formed on both sides of the silicon oxide layer 16 and the top surface of the silicon oxide layer 16 is also slightly higher than the top surfaces of the memory cell array region 110 and the peripheral circuit region 120

Due to the complicated steps of the boundary planarization process, the cost is high, and the residual height difference of the traditional processing method also increases the difficulty of the subsequent process and reduces the reliability of the product.

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