A kind of array substrate, its preparation method and display panel

A technology of array substrates and substrate substrates, which is applied in semiconductor/solid-state device manufacturing, instruments, semiconductor devices, etc., and can solve problems such as defects

Inactive Publication Date: 2019-07-12
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of this, an embodiment of the present invention provides an array substrate, its preparation method and a display panel, which are used to improve the bad problems caused by the via depth of the insulating layer in the existing array substrate.

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  • A kind of array substrate, its preparation method and display panel
  • A kind of array substrate, its preparation method and display panel
  • A kind of array substrate, its preparation method and display panel

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preparation example Construction

[0062] Based on the same inventive concept, an embodiment of the present invention also provides a method for preparing any one of the above-mentioned array substrates, such as Figure 6 As shown, the following steps may be included:

[0063] S601, forming a pattern of the first conductive layer on the base substrate;

[0064] S602, forming a pattern of an insulating layer on the base substrate formed with the first conductive layer; wherein, the insulating layer has a via area, a semi-reserved area outside the via area, and a pattern surrounding the semi-reserved area and the via area The fully reserved area of ​​the area, the via area is a via hole penetrating the insulating layer, and the vertical distance between the upper surface of the semi-reserved area of ​​the insulating layer and the upper surface of the first conductive layer is smaller than the upper surface of the fully reserved area of ​​the insulating layer the vertical distance from the upper surface of the fi...

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Abstract

The invention discloses an array substrate, a preparation method thereof and a display panel, comprising a substrate substrate, a first conductive layer, an insulating layer and a second conductive layer sequentially located on the substrate substrate, and the insulating layer has a via area, A semi-reserved area outside the via area, and a fully reserved area surrounding the area where the semi-reserved area and the via area are located. Since the via area is surrounded by a semi-reserved area, the thickness of the insulating layer around the via is reduced, and the size of the via can be reduced when the via slope is fixed, thereby increasing the aperture ratio and reducing the residual insulation at the edge of the via. The effect of layer material. In addition, since the height level difference of the insulating layer is divided into two levels, the influence of the level difference caused by the overall thickness of the insulating layer can be reduced.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate, its preparation method and a display panel. Background technique [0002] In the thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD) production process, since the organic insulating film layer is easy to form a thicker film layer, it can reduce signal interference in the array substrate, reduce parasitic capacitance, Due to the advantages of reducing substrate load and reducing power consumption, organic insulating films are widely used. Usually, the organic insulating film layer is disposed between two conductive film layers, for example, between the source-drain electrode layer and the pixel electrode layer. In order to electrically connect the pixel electrode to the drain of the thin film transistor, a via hole (Via Hole) needs to be formed on the organic insulating film layer. [0003] Such as Figure 1a Sh...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L27/12H01L21/77H01L21/768G02F1/1362
CPCG02F1/1362H01L21/768H01L21/76802H01L21/77H01L27/12H01L27/1214H01L27/02G02F1/136227H01L27/1244G02F1/134309G02F1/136259G02F1/136286H01L21/28008H01L27/1248H01L29/78633
Inventor陈程李纪龙徐德智吕艳明
OwnerBOE TECH GRP CO LTD