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Nonvolatile memory device employing thin film transistors and schottky diodes

A thin-film transistor and memory technology, applied in fields such as magnetic field-controlled resistors, can solve problems such as expensive MOS technology

Inactive Publication Date: 2016-04-20
TACHO HLDG LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Transistors Using MOS as selection elements limits the arrangement of existing MRAMs into three-dimensional configurations due to the longer interconnection from the far layer of the MTJ to the selection transistors
Also, MOS technology is relatively expensive

Method used

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  • Nonvolatile memory device employing thin film transistors and schottky diodes
  • Nonvolatile memory device employing thin film transistors and schottky diodes
  • Nonvolatile memory device employing thin film transistors and schottky diodes

Examples

Experimental program
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Effect test

no. 1 example

[0115] Figure 7 is a cross-sectional view of a three-dimensional memory array made according to a first embodiment of the present invention. The memory array (63) is based on Figure 6 A cross-point MRAM array is fabricated whereby a BBSD is incorporated into each memory element. A silicon wafer substrate (60) is provided with CMOS circuits (61) fabricated on the substrate. Such circuits are fabricated at a technology node (Fc), which may be the same size or smaller or larger than the technology node (Fm) used for the MTJ layer, depending on the nature of the CMOS circuit. For example, a microprocessor or a high-end FPGA can be fabricated at a smaller technology node Fc compared to an embedded memory array (Fm), which resides above the circuit. This embedded memory costs less than a separate chip and offers higher speeds because there is no delay to leave the chip. Lower power consumption is also achieved due to the reduction in circuitry. On the other hand, a standalone ...

no. 2 example

[0117] Figure 8 is a cross-sectional view of a three-dimensional memory array made according to a second embodiment of the present invention. The memory array (63) is based on Figure 6 A cross-point MRAM array is fabricated whereby a BBSD is incorporated into each memory element. A low cost glass substrate (70) is provided with a first thin film transistor layer (TFT-L1) circuit fabricated on the substrate. Such circuits are fabricated at a technology node (Ft) which may be the same size as the technology node (Fm) used for the MTJ layer, but preferably larger than Fm for cost savings. Such circuitry may include bandgap and decoder logic for the memory array (63), and select transistors for the first memory array (MTJ-L1). Additional circuitry for the memory arrays (MTJ-L1-MTJ-Ln) is provided in different additional layers (64) of thin film transistors (TFT-L1-TFT-Ln+1) arranged between the memory arrays. TFT circuits are fabricated at technology nodes (Ft) significantly ...

no. 3 example

[0119] Figure 9 is a cross-sectional view of a three-dimensional memory array made according to a third embodiment of the present invention. The memory array (63) is based on Figure 6 A cross-point MRAM array is fabricated whereby a BBSD is incorporated into each memory element. A low cost glass substrate (70) is provided with a first thin film transistor layer (TFT-L1) circuit fabricated on the substrate. Such circuits are fabricated at a technology node (Ft) which may be the same size as the technology node (Fm) used for the MTJ layer, but preferably larger than Fm for cost savings. Such circuitry may include bandgap and decoder logic for the memory array (63), and select transistors for the first memory array (MTJ-L1). Additional circuits for memory arrays (MTJ-L1-MTJ-Ln) are provided in different layers of thin film transistors (TFT-L2-TFT-L(n / 2+1)) arranged between every two memory arrays ( 64) inside. TFT circuits are fabricated at technology nodes (Ft) significant...

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PUM

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Abstract

An improved crosspoint memory array device comprising a plurality of memory cells is introduced. Each memory cell being is disposed at an intersection region of the conductive lines, where one of the first conductive lines is electrically coupled at a first terminal and one of the second conductive lines is electrically coupled at a second terminal. Each conductive line is electrically coupled to at least two thin film transistors (TFTs), which provide access to the memory cell. Each memory cell comprises an electrical resistance, which is controllable using a back to back Schottky diode, which is located between each memory cell and one of the said conductive lines. The device is substantially produced in BEOL facilities without the need of front end semiconductor production facilities, but can still be mad with ultra high density and at low cost.

Description

[0001] Cross references to related applications: [0002] This application claims priority from Provisional Patent Application Serial No. 61 / 699,211 having a filing date of September 10, 2012 and Provisional Patent Application Serial No. 61 / 702,485 having a subsequent filing date. [0003] Federally funded research: None. [0004] Sequence Listing: None. [0005] prior art literature [0006] US Patent Application Publication 2012 / 0281465, filed November 8, 2012 by Agan et al. [0007] US Patent Application Publication 2012 / 0257449 filed October 11, 2012 by Agan et al. [0008] Kim's US Patent No. 6,750,540, filed June 15, 2004. [0009] US Patent No. 5,640,343, filed June 17, 1997 by Gallagher et al. [0010] US Patent No. 7,224,601 filed May 29, 2007 by Panchula. [0011] US Patent No. 7,529,121 filed May 5, 2009 by Kitagawa et al. [0012] US Patent No. 6,838,721, filed January 4, 2005 by Garni et al. [0013] U.S. Patent No. 7,668,005 filed February 23, 2010 by Ueda....

Claims

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Application Information

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IPC IPC(8): H01L43/08
Inventor J·J·卢皮诺T·A·阿甘
Owner TACHO HLDG LLC