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Method for reducing interface stress in wafer bonding process

A technology of interface stress and wafer bonding, which is applied in the wafer bonding process to reduce interface stress. In the field of technology, it can solve problems such as thin wafer cracking, process failure, and broken, so as to reduce warpage and reduce Influence and reduce the effect of interface stress

Active Publication Date: 2016-05-04
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, if the subsequent thinning process is performed, cracking or breaking of the thin wafer will occur when the thickness reaches a certain level, resulting in process failure.

Method used

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  • Method for reducing interface stress in wafer bonding process
  • Method for reducing interface stress in wafer bonding process
  • Method for reducing interface stress in wafer bonding process

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Embodiment Construction

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings that are required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments described in the present invention, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

[0020] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0021] In order to effectively reduce the influence of the surface wafer 2 on the substrate wafer 1 and reduce the warpage after wafer bonding, the method for reducing interface stress of the present invention includes the following steps:

[0022] a. Provide a surface wafer 2 with a surface wafer active layer 4, and make grooves on the surface wafer active layer 4 of the surface wafer 2 to obtain...

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Abstract

The invention relate to a method for reducing interface stress in a wafer bonding process. The method comprises the following steps of (a) providing a surface wafer provided with a surface wafer active layer, and grooving the surface wafer active layer of the surface wafer to obtain a plurality of partition grooves passing through the surface wafer active layer, wherein the bottoms of the partition grooves are arranged in the surface wafer below the surface wafer active layer; (b) providing a substrate wafer for wafer bonding with the surface wafer, and bonding and fixing the substrate wafer and the surface wafer, wherein the substrate wafer is in contact with the surface wafer active layer of the surface wafer; and (c) thinning the back surface of the surface wafer until the bottoms of the partition grooves in the surface wafer are exposed. The method is simple in process step and is compatible with a traditional process, the influence of the surface wafer on the substrate wafer can be effectively reduced, the warpage of the wafers after bonding is reduced, and the method is safe and reliable.

Description

technical field [0001] The invention relates to a process method, in particular to a method for reducing interface stress in a wafer bonding process, and belongs to the technical field of semiconductor packaging. Background technique [0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the interconnection density of devices continues to increase. Therefore, wafer-level packaging (WaferLevelPackage, WLP) gradually replaces wire-bonding packaging and becomes a more commonly used packaging method. Wafer Level Packaging (WLP) technology is a technology for packaging and testing the entire wafer and then cutting it to obtain a single finished chip. Small, short, thin and low-cost requirements. [0003] Whether it is MEMS or CISBSI process, wafer-level packaging must use permanent bonding. At present, permanent bonding processes are generally divided into anodic bonding, metal fusion bonding, silicon oxide di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/18H01L21/02
CPCH01L21/02016H01L21/187
Inventor 冯光建
Owner NAT CENT FOR ADVANCED PACKAGING