Dither-free error feedback fractional-n frequency synthesizer system and method

Abstract

The fractional-N divider of the synthesizer is driven by a jitter-free error feedback modulator to mitigate the fractional spurt introduced by the cyclic string of the division ratio from the incremental accumulation modulator. The first feedback loop generates a feedback signal. The second feedback loop destroys the fractional spurious tone and the third feedback loop provides approximately zero static error.

Description

[0001] Merger by reference to any priority application [0002] Any and all applications filed with this application for which foreign or domestic priority claims are identified on the Application Information Sheet are hereby incorporated by reference pursuant to 37 CFR 1.57. technical field [0003] The present disclosure relates to a jitter-free delta-sigma modulator, a phase-locked loop (PLL) circuit, a wireless device, a method of operating a phase-locked loop (PLL) circuit in a frequency synthesizer of a wireless device, for use in multi-stage noise shaping ( A circuit arrangement used in a MASH modulator. Background technique [0004] A fractional-N frequency (fractional-N frequency) synthesizer is an essential component of any modern multiband and multistandard wireless transceiver system. These synthesizers use digital delta-sigma noise-shaping modulators to generate fractional division ratios. A delta-sigma modulator, however, includes a finite state machine that ...

AI Technical Summary

Problems solved by technology

However, in high-performance applications, dithering and seeding techniques are not useful because they significantly increase in-band noise and introduce large frequency errors

Images