36 results about "Spurious tone" patented technology

A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.

The present invention presents a method and a system for mitigating effects of clock harmonics in the receiver. The receiving signal may be monitored in such a way that the interfering harmonic component is tracked. When the interfering frequency is found out, the system determines the clock or clocks in the transceiver which are contributing to the interfering spurious tone. After that, the contributing clock(s) frequency is selected so that the effect of the spurious tone in the receiving passband is minimized or mitigated. This is performed by selecting a suitable clock frequency resulting in the spurious tones all falling outside the receiver passband; or in an OFDM system, by choosing a clock frequency deriving the spurious tone straight onto a subcarrier signal frequency.

Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.

Orthogonal frequency division multiplexing (OFDM) has become a popular transmission method for high speed wireless radio transmission, due to its potential for low complexity of transmitters and receivers. A method and apparatus are contemplated for cancelling additive sinusoidal disturbances of a known frequency in OFDM receivers which arise e.g. from clock signals that are present for frequency reference, mixer control, and A/D converter control, as well as harmonics and mixing products of those periodic signals, coupling into some point in the receiver chain and appearing as rotating complex exponentials superimposed to complex baseband receive signals. According to the inventive method and apparatus an estimation of an amplitude and phase of a disturbing superimposed tone with a known frequency is obtained and the amplitude and phase estimation is used to cancel the spurious tone preventing a degradation of receiver sensitivity while achieving low implementation complexity.

An artifact signal correction system may include a mixing component to generate a waveform corresponding to an artifact such as an error tone, whereupon that waveform may be combined with the input waveform to substantially eliminate the artifact. In preferred embodiments, a method and apparatus for reducing spurious tones in systems of mismatched interleaved digitizers due to interleave error is provided. In various embodiments the method may comprise reversing the frequency content of an input signal, converting the reversed signal into interleave artifact content, delaying the input signal along a parallel path, and then subtracting the interleave content from the delayed input signal.

An embodiment of the invention is a successive requantizer, which serves as a replacement for a ΔΣ modulator in a fractional-N PLL or a DAC, and avoids the above-mentioned spurious tone problem, thereby circumventing the tradeoffs that result from reliance on common approach of making highly linear analog circuitry to avoid spurious tones. A successive requantizer fractional-N PLL of the invention has the potential to reduce power consumption and the cost of commercial communication devices. A successive requantizer of the invention performs digital quantization one bit at a time in such a way that the quantization noise can be engineered to have desirable properties such as non-linearity robustness. The invention is applicable to most high-performance digital communication systems, such as cellular telephone handsets and wireless local and metropolitan area network transceivers.

In an embodiment, a delta-sigma modulator is constructed from one or more stages of a first order low-pass filter, which has a modest gain compared to the integrator used in other embodiments of delta-sigma modulators. Delta-sigma modulators can be converted into low-pass filter based delta-sigma modulators according to an embodiment of the invention by replacing the ideal integrator building block with a first order low-pass filter and adjusting other loop parameters, such as gain factors, accordingly. In an embodiment, a dithering technique to suppress spurious tones can be used with the low-pass filter based, ideal integrator based, or near ideal integrator based delta-sigma modulator. In another embodiment, a noise cancellation technique can also be used to cancel the dithering noise.

The invention provides dither-less error feedback fractional-n frequency synthesizer systems and methods. A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from deita-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.

In an embodiment, a delta-sigma modulator is constructed from one or more stages of a first order low-pass filter, which has a modest gain compared to the integrator used in other embodiments of delta-sigma modulators. Delta-sigma modulators can be converted into low-pass filter based delta-sigma modulators according to an embodiment of the invention by replacing the ideal integrator building block with a first order low-pass filter and adjusting other loop parameters, such as gain factors, accordingly. In an embodiment, a dithering technique to suppress spurious tones can be used with the low-pass filter based, ideal integrator based, or near ideal integrator based delta-sigma modulator. In another embodiment, a noise cancellation technique can also be used to cancel the dithering noise.

Described embodiments provide an interleaved sampler having N sample and hold circuits for sampling an input signal, and M multiplexers. Each multiplexer is adapted to couple all N of the plurality of sample and hold circuits to a respective output of the interleaved sampler. The interleaved sampler samples at a sample rate of f_s, has an interleaved sampling period of M/f_s, where M is greater than one and less than N. Because there are more sample and hold circuits than there are samples taken during an interleaved sampling period, different combinations of the sample and hold circuits are used from interleaved sample period to interleaved sample period. This reduces spurious tones generated from offset voltages when using interleaved sample and hold circuits. The order of the sample and hold circuits are clocked might be random, pseudorandom, or a fixed pattern longer than the interleaved sampling period.

An electrical circuit (10) is provided. The electrical circuit can have an input terminal (12) to receive an input signal and an output terminal (20) at which an output signal can be provided. The electrical circuit further comprises, a local oscillator (14), a first mixer (16), a second mixer (18), and a delay element (22). In the electrical circuit the first mixer is configured to receive an input signal from the input terminal and to mix the input signal with a local oscillator signal. Also, the second mixer is configured to receive said input signal from the input terminal and to mix the input signal with a delayed local oscillator signal, where the delayed local oscillator signal is said local oscillator signal fed via the delay element to the second mixer. The electrical circuit is configured to combine the output signal from the first mixer with the output signal from the second mixer to form an output signal at the output terminal. Hereby, an electrical circuit is provided thatcan efficiently handle the non-idealities of a local oscillator, LO, signal in receivers or transmitters. This is achieved by the electrical circuit that uses a form of finite impulse response, FIR,filter mixer. For example, in receivers, the electrical circuit can be used to filter harmonic components of a pulse-shaped LO signal, resulting in attenuation of the unwanted harmonic down-conversionproducts. The electrical circuit can also be used in other applications, such as but not limited to, filtering of the quantization noise or spurious tones of a digitally generated LO signal.