Circuit structure for phase-locked loop

Abstract

The invention provides a circuit structure for a phase-locked loop. The circuit structure comprises charge pumps of an upper branch current source and a lower branch current source and a phase inverter; a first switching tube is arranged at a lower branch and is controlled and is connected to the output terminal of the phase inverter; a control signal is connected with the input terminal of the phase inverter; and a second switching tube is connected with the control signal and is controlled by the control signal. The second switching tube is connected with a bias current source; and a branch circuit formed by the second switching tube and the bias current source is connected in parallel to the lower branch of the charge pump. According to the invention, a high-linearity low-noise charge pump circuit is provided; switching between a locking state and a non-locking state of the phase-locked loop can be carried out; and the charge pump has a typical working mode and a high-linearity and low-noise working mode. According to the circuit structure, the best charge pump performance can be obtained and no influence is caused on the locking time of the phase-locked loop.

Description

technical field [0001] The invention relates to the field of communication equipment, in particular to a circuit structure used in a phase-locked loop circuit to improve the linearity of a charge pump transfer function. Background technique [0002] The phase-locked loop (PLL) is the core circuit in various communication and clock chips. The spectral noise, jitter, spurious and other indicators of the output signal are very critical and will directly affect the system performance. The charge pump (CP) is an important module in the PLL, and its output current generates the control voltage of the voltage-controlled oscillator (VCO) after passing through the loop filter. The noise performance of the CP output signal is very important, which determines the in-band noise floor (NoiseFloor) of the entire PLL and the jitter of the PLL output clock. [0003] The charge pump converts the phase signal output by the phase frequency detector (PFD) into a current signal. The ideal CP in...

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Problems solved by technology

[0010] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of circuit structure for phase-locked loop, be used for solving the non-linear characteristic of charge pump when phase difference of phase-locked loop is close to 0 in the prior art Issues that degrade PLL in-band noise and degrade spurious performance at the PLL reference frequency

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