A method and device for reducing dtls decryption delay
A delay and decryption technology, applied in the field of DTLS decryption, can solve the problems of increased CPU load, memory consumption, large decryption delay, etc., to achieve the effect of reducing processing time, reducing chip cost, and reducing storage area
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[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.
[0033] A method and device for reducing the delay of DTLS decryption disclosed by the present invention optimize the serial flow of first decryption and then authentication on the premise that the chip level supports the DTLS decryption algorithm, so that the decryption and authentication processes can be operated in parallel, Therefore, the processing time of DTLS decryption is reduced, and the ability of the switch chip to process CAPWAP ciphertext is increased. At the same time, under this mechanism, the DTLS decryption module does not need to store the entire message, thereby reducing the storage area and chip cost.
[0034] After analysis, in the CAPWAP ciphertext, the length field in the DTLS header includes a 16-byte IV field, a CAPWAP header, CAPWAP valid data, a 20-byte HMAC,...
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