Well isolation type anti-SEU multi-node overturning storage unit layout structure
A storage unit and layout structure technology, applied in electrical components, transistors, electric solid-state devices, etc., can solve the problems of ordinary DICE storage unit flipping, improve anti-SEU performance, reduce the probability of multi-node flipping, and increase the distance Effect
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[0026] The invention overcomes the disadvantage that common DICE memory cells in the ultra-deep sub-micron process will cause multiple storage nodes in the unit to flip under the influence of SEU, and eventually lead to the flipping of common DICE memory cells, and proposes a new well-isolated anti-corrosion The SEU multi-node flip memory cell layout structure can effectively separate all sensitive node pairs in the common DICE memory cell structure and increase the distance between sensitive node pairs. Among them, for PMOS transistors, N-well isolation can effectively stabilize the N-well voltage. Reduces the chance of flipping multiple storage nodes due to parasitic bipolar transistor effects. For NMOS transistors, the N-well isolation effectively shunts the holes generated by incoming particles, reducing the occurrence of multiple storage nodes due to charge sharing effects. The probability of flipping, thereby suppressing the multi-node flipping caused by SEU in the DICE u...
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