Latch and frequency divider

[0079] See figure 1 As shown, the high-speed frequency divider in the prior art may include latches 101 and 102, where the latches 101 and 102 are mutually subsequent units.

[0080] The output signal frequency of the high-speed two-frequency divider is 1/2 of the input signal frequency, which can realize the output of the quadrature frequency division signal with 25% or 75% duty cycle.

[0081] figure 2 The schematic diagram of the circuit structure of the latch in the high-speed two-frequency divider that realizes the frequency division signal with the duty cycle of 75% is shown. See figure 2 Shown. The latch 200 includes a first logic unit 201 and a second logic unit 202 coupled between a power supply and a ground.

[0082] The first logic unit 201 has a first control terminal CLK1, a first signal input terminal D, and a first signal output terminal Qn, and the second logic unit has a second control terminal CLK2, a second signal input terminal Dn, and a second signal output terminal Q .

[0083] The first logic unit 201 includes a first transistor M1, a third transistor M3, and a fifth transistor M5. The second logic unit 202 includes a second transistor M2, a fourth transistor M4, and a sixth transistor M6. The first transistor M1 and the second transistor M2 are NMOS transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all PMOS transistors, in which:

[0084] The source terminals of the first transistor M1 and the second transistor M2 are respectively coupled to the ground line VREF_2. The gate terminals of the first transistor M1 and the second transistor M2 are respectively coupled to the first control terminal CLK1 and the second control terminal CLK2. The drain terminal of the transistor M1 is respectively coupled to the drain terminal of the third transistor M3 and the fifth transistor M5, and the first output terminal Qn and the gate terminal of the fourth transistor M4. The drain terminal of the second transistor M2 is respectively coupled to the fourth transistor M4. The drain terminals of the transistor M4 and the sixth transistor M6, and the second output terminal Q are coupled to the gate terminal of the third transistor M3, and the source terminals of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 It is coupled to the power supply VREF_1.

[0085] When the first control terminal CLK1 and the second control terminal CLK2 are both at a high level (VREF_3), the first transistor M1 and the second transistor M2 are turned on. At this time, if a low level is input to the first input terminal D and a high level is input to the second input terminal Dn, the fifth transistor M5 is turned on, and the sixth transistor M6 is turned off, and the third transistor M3 is turned on at the same time , The fourth transistor M4 is turned off. At this time, there is a DC path from the power supply VREF_1, the third transistor M3/fifth transistor M5, the first transistor M1 to VREF_2, and the latch has DC power consumption.

[0086] When the first control terminal CLK1 and the second control terminal CLK2 are both at low level (VREF_4), the first transistor M1 and the second transistor M2 are turned off, and the second output terminal Q and the first output terminal Qn of the latch are respectively The fifth transistor M5 and the sixth transistor M6 are charged so that the second output terminal Q and the first output terminal Qn are close to the level of the power supply VREF_1.

[0087] When the CLK is under the dynamic condition, the corresponding latch also has a current path from the power supply VREF_1 to the ground line VREF_2, which increases the dynamic power consumption of the latch.

[0088] Therefore, the latches used in the high-speed frequency divider in the prior art have static power consumption and dynamic power consumption under static working conditions and dynamic working conditions, respectively, which severely restricts the application of the high-speed frequency divider.

[0089] In order to solve the above-mentioned problems in the prior art, the technical solution adopted in the embodiment of the present invention adopts an input feedforward control unit to control the coupling between the ground wires of the power supply according to the differential signal input from the first input terminal and the second input terminal. The current path is closed, therefore, the power consumption of the latch under static working conditions can be eliminated, and the dynamic power consumption under dynamic working conditions can be reduced at the same time.

[0090] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0091] image 3 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as image 3 The latch 300 shown may include a first logic unit 301 coupled between the power supply VREF_1 and the ground line VREF_2, a second logic unit 302 having a structure symmetrical to the first logic unit 301, and an input feedforward control Unit 303, where:

[0092] The first logic unit 301 has a first control terminal CLK1, a first input terminal D, and a first output terminal Qn; the second logic unit 302 has a second control terminal CLK2, a second input terminal Dn, and a second output terminal Q.

[0093] The input feedforward control unit 303 is adapted to control the closing of the current path in the first logic unit 301 or the second logic unit 302 according to the input signal Dn input to the first input terminal D and the second input terminal.

[0094] Figure 4 It shows a schematic structural diagram of an input feedforward control unit in an embodiment of the present invention. Such as Figure 4 The shown input feedforward control unit 400 may include at least one of a first control subunit 401 and a second control subunit 402, wherein:

[0095] The first control subunit 401 is adapted to turn off the current in the first logic unit 101 when the signals input by the first input terminal D and the second input terminal Dn are low and high respectively path.

[0096] The second control subunit 402 is adapted to turn off the current in the second logic unit 102 when the signals input by the first input terminal D and the second input terminal Dn are high and low respectively path.

[0097] Figure 5 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Figure 5 The latch shown may include a first logic unit, a second logic unit and a first control sub-unit, where the first control sub-unit may include a seventh transistor M7.

[0098] Please continue to see figure 2 As shown, Figure 5 The structure of the latch shown in figure 2 A seventh transistor M7 is added to the structure of the latch shown in the figure. The seventh transistor M7 is an NMOS tube, where:

[0099] The source terminal of the seventh transistor M7 is coupled to the drain terminal of the first transistor M1, the gate terminal is coupled to the first input terminal D, and the drain terminal is coupled to the drain terminal of the third transistor M3 and the fifth transistor M5, and the fourth transistor The gate terminal of M4 is coupled to the first output terminal Qn.

[0100] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, and the fourth transistor M4 and the sixth transistor M6 are turned off, thereby turning off the power supply VREF_1, the third transistor M3/the fifth transistor in the first logic unit The DC path between the transistor M5, the first transistor M1 and the VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated, and the dynamic power consumption can be greatly reduced. Power consumption.

[0101] Image 6 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Image 6 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit. The first control sub-unit may include a seventh transistor M7 and an eighth transistor M8, and a seventh transistor M7 and a The eight transistors M8 are all NMOS transistors.

[0102] Please continue to see Figure 5 As shown, Image 6 The latch shown is in Figure 5 An eighth transistor M8 is added to the latch shown, in which:

[0103] The source terminal of the eighth transistor M8 is coupled to the drain terminal of the second transistor M2, the gate terminal is coupled to the second input terminal Dn, and the drain terminal is coupled to the drain terminal of the fourth transistor M4 and the sixth transistor M6, and the drain terminal of the third transistor M3. The gate terminal is coupled to the second output terminal Q.

[0104] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, the fourth transistor M4 and the sixth transistor M6 are turned off, and the eighth transistor M8 is turned on, thereby turning on the power supplies VREF_1, The DC path between the third transistor M3/fifth transistor M5, the first transistor M1 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static state of the latch can be eliminated. Power consumption, and greatly reduce dynamic power consumption.

[0105] Figure 7 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Figure 7 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit. The first control sub-unit may include a seventh transistor M7 and an eighth transistor M8, and a seventh transistor M7 and a The eight transistors M8 are all NMOS transistors.

[0106] Please continue to see Image 6 As shown, Figure 7 The structure of the latch shown in Image 6 The source terminals of the seventh transistor M7 and the eighth transistor M8 are coupled together based on the structure of the latch shown in FIG.

[0107] Similarly, when the first control terminal CLK1 and the second control terminal CLK2 are both at a high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low voltage respectively. At a high level, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, the fourth transistor M4 and the sixth transistor M6 are turned off, and the eighth transistor M8 is turned on, thereby turning on the first logic unit. The DC path between the power supply VREF_1, the third transistor M3/fifth transistor M5, and the first transistor M1 to VREF_2 is closed. Therefore, the latching can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both at a high level. The static power consumption of the device, and greatly reduce the dynamic power consumption.

[0108] Figure 8 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 8 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit. The first control sub-unit may include a seventh transistor M7, and the seventh transistor M7 is an NMOS transistor.

[0109] Please continue to see figure 2 As shown, Figure 8 The latch shown is in figure 2 A seventh transistor M7 is added to the latch shown, in which:

[0110] The source terminal of the seventh transistor M7 is coupled to the ground line VREF_2, the gate terminal is coupled to the first input terminal D, and the drain terminal is coupled to the source terminal of the first transistor M1.

[0111] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the inputs of the first input terminal D and the second input terminal Dn are input with low level and high level respectively. Level, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, and the fourth transistor M4 and the sixth transistor M6 are turned off, thereby turning off the power supply VREF_1 and the third transistor M3/th in the first logic unit. The DC path between the five-transistor M5, the first transistor M1 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated, and the static power consumption of the latch can be greatly reduced. Dynamic power consumption.

[0112] Picture 9 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Picture 9 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit. The first control sub-unit may include a seventh transistor M7 and an eighth transistor M8, and a seventh transistor M7 and a The eight transistors M8 are all NMOS transistors.

[0113] Please continue to see Figure 8 As shown, Picture 9 The latch is in Figure 8 An eighth transistor M8 is added to the latch shown, in which:

[0114] The source terminal of the eighth transistor M8 is coupled to the ground line VREF_2, the gate terminal is coupled to the second input terminal D, and the drain terminal is coupled to the source terminal of the second transistor M2.

[0115] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, the fourth transistor M4 and the sixth transistor M6 are turned off, and the eighth transistor M8 is turned on, thereby turning on the power supplies VREF_1, The DC path between the third transistor M3/fifth transistor M5, the first transistor M1 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static state of the latch can be eliminated. Power consumption, and greatly reduce dynamic power consumption.

[0116] Picture 10 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Picture 10 The latch shown may include a first logic unit, a second logic unit and a first control sub-unit, where the first control sub-unit may include a seventh transistor M7.

[0117] Please continue to see figure 2 As shown, Picture 10 The structure of the latch shown in figure 2 A seventh transistor M7 is added to the structure of the latch shown in FIG. The seventh transistor M7 is a PMOS tube, where:

[0118] The drain terminal of the seventh transistor M7 is coupled to the drain terminal of the first transistor M1, the gate terminal is coupled to the second input terminal Dn, and the source terminal is coupled to the drain terminal of the third transistor M3 and the fifth transistor M5, and the fourth transistor M4. The gate terminal is coupled to the first output terminal Qn.

[0119] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, and the fourth transistor M4 and the sixth transistor M6 are turned off, thereby turning off the power supply VREF_1, the third transistor M3/the fifth transistor in the first logic unit The DC path between the transistor M5, the first transistor M1 and the VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated, and the dynamic power consumption can be greatly reduced. Power consumption.

[0120] Picture 11 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Picture 11 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit, where the first control sub-unit may include a seventh transistor and an eighth transistor, and a seventh transistor M7 and an eighth transistor M8 is a PMOS tube.

[0121] Please continue to see Picture 10 As shown, Picture 11 The structure of the latch shown in Picture 10 An eighth transistor M8 is added to the structure of the latch shown in, where:

[0122] The drain terminal of the eighth transistor M8 is coupled to the drain terminal of the second transistor M2, the gate terminal is coupled to the first input terminal D, and the source terminal is coupled to the drain terminal of the fourth transistor M4 and the sixth transistor M6, and the third transistor M3. The gate terminal is coupled to the second output terminal Q.

[0123] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, the fourth transistor M4 and the sixth transistor M6 are turned off, and the eighth transistor M8 is turned on, thereby turning on the power supplies VREF_1, The DC path between the third transistor M3/fifth transistor M5, the first transistor M1 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static state of the latch can be eliminated. Power consumption, and greatly reduce dynamic power consumption.

[0124] Picture 12 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Picture 12 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit. The first control sub-unit may include a seventh transistor M7 and an eighth transistor M8, and a seventh transistor M7 and a The eight transistors M8 are all PMOS tubes.

[0125] Please continue to see Picture 11 As shown, Picture 12 The structure of the latch shown in Picture 11 Based on the structure of the latch shown in the figure, the drain terminals of the seventh transistor M7 and the eighth transistor M8 are coupled together.

[0126] When the first control terminal CLK1 and the second control terminal CLK2 are both at a high level, the first transistor M1 and the second transistor M2 are turned on, and when the first input terminal D and the second input terminal Dn input a low level and a high level, respectively , The third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, the fourth transistor M4 and the sixth transistor M6 are turned off, and the eighth transistor M8 is turned on, thereby turning on the power supply VREF_1 and the second transistor in the first logic unit. The DC path between the three transistors M3/fifth transistor M5, the first transistor M1 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static function of the latch can be eliminated. And greatly reduce dynamic power consumption.

[0127] Figure 13 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Picture 12 The latch shown may include a first logic unit, a second logic unit and a first control sub-unit, where the first control sub-unit may include a seventh transistor M7, and the seventh transistor M7 is a PMOS transistor.

[0128] Please continue to see figure 2 As shown, Figure 13 The structure of the latch shown in figure 2 A seventh transistor M7 is added to the structure of the latch shown in, in which:

[0129] The drain terminal of the seventh transistor M7 is coupled to the ground line VREF_2, the gate terminal is coupled to the second input terminal Dn, and the source terminal is coupled to the source terminal of the first transistor M1.

[0130] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, and the fourth transistor M4 and the sixth transistor M6 are turned off, thereby turning off the power supply VREF_1, the third transistor M3/the fifth transistor in the first logic unit The DC path between the transistor M5, the first transistor M1 and the VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated, and the dynamic power consumption can be greatly reduced. Power consumption.

[0131] Figure 14 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 14 The latch shown may include a first logic unit, a second logic unit, and a first control sub-unit. The second control sub-unit may include a seventh transistor M7 and an eighth transistor M8, and a seventh transistor M7 and a The eight transistors M8 are all PMOS tubes.

[0132] Please continue to see Figure 13 As shown, Figure 14 The structure of the latch shown in Figure 13 An eighth transistor M8 is added to the structure of the latch shown in, where:

[0133] The drain terminal of the eighth transistor M8 is coupled to the ground line VREF_2, the gate terminal is coupled to the first input terminal D, and the source terminal is coupled to the source terminal of the second transistor M2.

[0134] When the first control terminal CLK1 and the second control terminal CLK2 are both high, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with a low level and a high level respectively. Usually, the third transistor M3 and the fifth transistor M5 are turned on, the seventh transistor M7 is turned off, the fourth transistor M4 and the sixth transistor M6 are turned off, and the eighth transistor M8 is turned on, thereby turning on the power supplies VREF_1, The DC path between the third transistor M3/fifth transistor M5, the first transistor M1 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static state of the latch can be eliminated. Power consumption, and greatly reduce dynamic power consumption.

[0135] Figure 15 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 15 The latch shown may include a first logic unit, a second logic unit, and a second control subunit. The third control subunit may include a ninth transistor M9, and the ninth transistor M9 is an NMOS transistor.

[0136] Please continue to see figure 2 As shown, Figure 15 The structure of the latch shown in figure 2 A ninth transistor M9 is added to the structure of the latch shown in, in which:

[0137] The source terminal of the ninth transistor M9 is coupled to the drain terminal of the second transistor M2, the gate terminal is coupled to the second input terminal Dn, and the drain terminal is coupled to the drain terminal of the fourth transistor M4 and the sixth transistor M6, and the drain terminal of the third transistor M3. The gate terminal is coupled to the second output terminal Q.

[0138] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, and the third transistor M3 and the fifth transistor M5 are turned off, thereby turning off the power supply VREF_1 and the fourth transistor M4/sixth transistor M4 in the second logic unit. The DC path between the transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated and the dynamic power consumption can be greatly reduced. Power consumption.

[0139] Figure 16 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 16 The latch shown may include a first logic unit, a second logic unit, and a second control subunit. The second control subunit may include a ninth transistor M9 and a tenth transistor M10, and a ninth transistor M9 and a second control subunit. The ten transistors M10 are all NMOS transistors.

[0140] Please continue to see Figure 15 As shown, Figure 16 The structure of the latch shown in Figure 15 A tenth transistor M10 is added to the structure of the latch shown in, where:

[0141] The source terminal of the tenth transistor M10 is coupled to the drain terminal of the first transistor M1, the gate terminal is coupled to the first input terminal D, and the drain terminal is coupled to the drain terminal of the third transistor M3 and the fifth transistor M5, and the drain terminal of the fourth transistor M3. The gate terminal is coupled to the first output terminal Qn.

[0142] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, the third transistor M3 and the fifth transistor M5 are turned off, and the tenth transistor M10 is turned on, thereby turning on the power supplies VREF_1, The DC path between the fourth transistor M4/sixth transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, the static state of the latch can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both high level. Power consumption, and greatly reduce dynamic power consumption.

[0143] Figure 17 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 17 The latch shown may include a first logic unit, a second logic unit, and a second control subunit. The second control subunit may include a ninth transistor M9 and a tenth transistor M10, and a ninth transistor M9 and a second control subunit. The ten transistors M10 are all NMOS transistors.

[0144] Please continue to see Figure 16 As shown, Figure 17 The structure of the latch shown in Figure 16 Based on the latch, the drain terminals of the ninth transistor M9 and the tenth transistor M10 are coupled together.

[0145] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, the third transistor M3 and the fifth transistor M5 are turned off, and the tenth transistor M10 is turned on, thereby turning on the power supplies VREF_1, The DC path between the fourth transistor M4/sixth transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, the static state of the latch can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both high level. Power consumption, and greatly reduce dynamic power consumption.

[0146] Figure 18 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 18 The latch shown may include a first logic unit, a second logic unit, and a second control subunit. The second control subunit may include a ninth transistor M9, and the ninth transistor M9 is a PMOS transistor.

[0147] Please continue to see figure 2 As shown, Figure 18 The structure of the latch shown in figure 2 Nine transistors M9 are added to the structure of the latch shown in, among them:

[0148] The source terminal of the ninth transistor M9 is coupled to the ground line VREF_2, the gate terminal is coupled to the second input terminal Dn, and the drain terminal is coupled to the source terminal of the second transistor M2.

[0149] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, and the third transistor M3 and the fifth transistor M5 are turned off, thereby turning off the power supply VREF_1 and the fourth transistor M4/sixth transistor M4 in the second logic unit. The DC path between the transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated and the dynamic power consumption can be greatly reduced. Power consumption.

[0150] Figure 19 It shows a schematic structural diagram of another latch in the embodiment of the present invention. Such as Figure 19 The latch shown may include a first logic unit, a second logic unit, and a second control subunit. The second control subunit may include a ninth transistor M9 and a tenth transistor M10, and a ninth transistor M9 and a second control subunit. The ten transistors M10 are all NMOS transistors.

[0151] Please continue to see Figure 19 As shown, Figure 19 The structure of the latch shown in Figure 18 A tenth transistor M10 is added to the structure of the latch shown in, where:

[0152] The source terminal of the tenth transistor M10 is coupled to the ground line VREF_2, the gate terminal is coupled to the first input terminal D, and the drain terminal is coupled to the source terminal of the first transistor M1.

[0153] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, the third transistor M3 and the fifth transistor M5 are turned off, and the tenth transistor M10 is turned on, thereby turning on the power supplies VREF_1, The DC path between the fourth transistor M4/sixth transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, the static state of the latch can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both high level. Power consumption, and greatly reduce dynamic power consumption.

[0154] Picture 20 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Picture 20 The latch shown may include a first logic unit, a second logic unit and a second control sub-unit, where the second control sub-unit may include a ninth transistor M9.

[0155] Please continue to see figure 2 As shown, Picture 20 The structure of the latch shown in figure 2 A ninth transistor M9 is added to the structure of the latch shown in the figure. The ninth transistor M9 is a PMOS tube, where:

[0156] The drain terminal of the ninth transistor M9 is coupled to the drain terminal of the second transistor M2, the gate terminal is coupled to the first input terminal D, and the drain terminal is coupled to the drain terminal of the fourth transistor M4 and the sixth transistor M6, and the third transistor M3. The gate terminal is coupled to the second output terminal Q.

[0157] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, and the third transistor M3 and the fifth transistor M5 are turned off, thereby turning off the power supply VREF_1 and the fourth transistor M4/sixth transistor M4 in the second logic unit. The DC path between the transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated and the dynamic power consumption can be greatly reduced. Power consumption.

[0158] Figure 21 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Figure 21 The latch shown may include a first logic unit, a second logic unit, and a second control sub-unit. The second control sub-unit may include a ninth transistor M9 and a tenth transistor M10, and a ninth transistor M9 and a second control sub-unit. The ten transistors M10 are all PMOS tubes.

[0159] Please continue to see Picture 20 As shown, Figure 21 The structure of the latch shown in Picture 20 A tenth transistor M10 is added to the structure of the latch shown in, where:

[0160] The drain terminal of the tenth transistor M10 is coupled to the drain terminal of the first transistor M1, the gate terminal is coupled to the second input terminal Dn, and the source terminal is coupled to the drain terminal of the third transistor M3 and the fifth transistor M5, and the fourth transistor M4 The gate terminal is coupled to the first output terminal Qn.

[0161] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, the third transistor M3 and the fifth transistor M5 are turned off, and the tenth transistor M10 is turned on, thereby turning on the power supplies VREF_1, The DC path between the fourth transistor M4/sixth transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, the static state of the latch can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both high level. Power consumption, and greatly reduce dynamic power consumption.

[0162] Figure 22 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Figure 22 The latch shown may include a first logic unit, a second logic unit and a fourth control sub-unit, where the fourth control sub-unit may include a thirteenth transistor M13 and a fourteenth transistor M14.

[0163] Please continue to see Figure 21 As shown, Figure 22 The structure of the latch shown in Figure 21 The source terminals of the ninth transistor M9 and the tenth transistor M10 are coupled together based on the structure of the latch shown in FIG.

[0164] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, the third transistor M3 and the fifth transistor M5 are turned off, and the tenth transistor M10 is turned on, thereby turning on the power supplies VREF_1, The DC path between the fourth transistor M4/sixth transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, the static state of the latch can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both high level. Power consumption, and greatly reduce dynamic power consumption.

[0165] Figure 23 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Figure 23 The latch shown may include a first logic unit, a second logic unit and a second control sub-unit, where the second control sub-unit may include a ninth transistor M9.

[0166] Please continue to see figure 2 As shown, Figure 23 The structure of the latch shown in figure 2 A ninth transistor M9 is added to the structure of the latch shown in the figure. The ninth transistor M9 is a PMOS tube, where:

[0167] The source terminal of the ninth transistor M9 is coupled to the ground line VREF_2, the gate terminal is coupled to the first input terminal D, and the drain terminal is coupled to the source terminal of the second transistor M2.

[0168] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, and the third transistor M3 and the fifth transistor M5 are turned off, thereby turning off the power supply VREF_1 and the fourth transistor M4/sixth transistor M4 in the second logic unit. The DC path between the transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, when the first control terminal CLK1 and the second control terminal CLK2 are both high, the static power consumption of the latch can be eliminated and the dynamic power consumption can be greatly reduced. Power consumption.

[0169] Figure 24 It shows a schematic structural diagram of a latch in an embodiment of the present invention. Such as Figure 24 The latch shown may include a first logic unit, a second logic unit, and a second control sub-unit. The second control sub-unit may include a ninth transistor M9 and a tenth transistor M10, and a ninth transistor M9 and a second control sub-unit. The ten transistors M10 are all PMOS tubes.

[0170] Please continue to see Figure 23 As shown, Figure 24 The structure of the latch shown in Figure 23 A fourteenth transistor M14 is added to the structure of the latch shown in the following:

[0171] The drain terminal of the tenth transistor M10 is coupled to the ground line VREF_2, the gate terminal is coupled to the second input terminal Dn, and the source terminal is coupled to the source terminal of the first transistor M1.

[0172] When the first control terminal CLK1 and the second control terminal CLK2 are both at high level, the first transistor M1 and the second transistor M2 are turned on, and the first input terminal D and the second input terminal Dn are inputted with high level and low level respectively. Usually, the fourth transistor M4 and the sixth transistor M6 are turned on, the ninth transistor M9 is turned off, the third transistor M3 and the fifth transistor M5 are turned off, and the tenth transistor M10 is turned on, thereby turning on the power supplies VREF_1, The DC path between the fourth transistor M4/sixth transistor M6, the second transistor M2 and VREF_2 is closed. Therefore, the static state of the latch can be eliminated when the first control terminal CLK1 and the second control terminal CLK2 are both high level. Power consumption, and greatly reduce dynamic power consumption.

[0173] The embodiment of the present invention also provides a frequency divider, including at least two latches described above, wherein the first input terminal and the second input terminal of any one of the two latches are connected to the other The first output terminal and the second output terminal of a latch are respectively coupled.

[0174] The method and system of the embodiments of the present invention have been described in detail above, and the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.