Latch and frequency divider

A technology of latches and transistors, applied in the direction of synchronous pulse counters, pulse technology, logic circuits, etc., can solve the problem of large power consumption, and achieve the effect of eliminating power consumption and reducing dynamic power consumption

Active Publication Date: 2016-06-01
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, when the control signal input by the control terminal of the latch of the high-speed frequency divider circuit in the prior art is at a low level, no matter it is in a static working condition or in a dynamic worki

Method used

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  • Latch and frequency divider
  • Latch and frequency divider
  • Latch and frequency divider

Examples

Experimental program
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Example Embodiment

[0079] See figure 1 As shown, the high-speed frequency divider in the prior art may include latches 101 and 102, where the latches 101 and 102 are mutually subsequent units.

[0080] The output signal frequency of the high-speed two-frequency divider is 1 / 2 of the input signal frequency, which can realize the output of the quadrature frequency division signal with 25% or 75% duty cycle.

[0081] figure 2 The schematic diagram of the circuit structure of the latch in the high-speed two-frequency divider that realizes the frequency division signal with the duty cycle of 75% is shown. See figure 2 Shown. The latch 200 includes a first logic unit 201 and a second logic unit 202 coupled between a power supply and a ground.

[0082] The first logic unit 201 has a first control terminal CLK1, a first signal input terminal D, and a first signal output terminal Qn, and the second logic unit has a second control terminal CLK2, a second signal input terminal Dn, and a second signal output te...

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PUM

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Abstract

The invention provides a latch and a frequency divider. The latch comprises a first logic unit coupled between a power supply and a ground wire, a second logic unit in structure symmetry with the first logic unit, and an input feedforward control unit, wherein the first logic unit is provided with a first control end, a first input end and a first output end; the second logic unit is provided with a second control end, a second input end and a second output end; and the input feedforward control unit is suitable for controlling the closing of a current channel in the first logic unit or the second logic unit according to input signals of the first input end and the second input end. By adopting the above scheme, the power consumption of the latch under a static work condition is eliminated, and the dynamic power consumption under a dynamic work condition is simultaneously lowered.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a latch and a frequency divider. Background technique [0002] With the development of communication technology, the high-speed frequency divider based on the razavi structure latch has been widely used because of its advantages of fast speed and wide bandwidth. [0003] The high-speed frequency divider circuit for frequency division by two is composed of two stages of latches, any one of which is the subsequent unit of the other latch. [0004] However, when the control signal input by the control terminal of the latch of the high-speed frequency divider circuit in the prior art is at a low level, no matter it is under static working conditions or under dynamic working conditions, there is a power-to-ground fault. current path between wires. It can be seen from the above that the latches used in the high-speed frequency divider circuit in the prior art have the problem ...

Claims

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Application Information

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IPC IPC(8): H03K19/0944H03K21/00
CPCH03K3/356139H03K3/356191H03K23/40H03K5/04
Inventor 吴毅强
Owner SPREADTRUM COMM (SHANGHAI) CO LTD
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