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Semiconductor chip packaging structure and packaging method thereof

A technology of chip packaging structure and packaging method, which is applied in the direction of semiconductor devices, electric solid devices, radiation control devices, etc., can solve problems affecting the quality of finished chips, support structure 101 layered cracking, etc., to solve layered cracking and reduce impact force effect

Active Publication Date: 2020-03-24
CHINA WAFER LEVEL CSP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, in the reliability test, the support structure 101 may appear delamination and cracking, which affects the quality of the finished chip, and becomes a problem to be solved by those skilled in the art.

Method used

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  • Semiconductor chip packaging structure and packaging method thereof
  • Semiconductor chip packaging structure and packaging method thereof
  • Semiconductor chip packaging structure and packaging method thereof

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Embodiment Construction

[0029] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.

[0030] It should be noted that the purpose of providing these drawings is to facilitate the understanding of the embodiments of the present invention, and should not be interpreted as undue limitations on the present invention. For clarity, the dimensions shown in the figures are not drawn to scale and may be enlarged, reduced or otherwise changed. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

[0031] The preferred embodiment of the present invention takes an image sensor chip as an example. Of course, the present invention is not li...

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Abstract

The present invention provides a semiconductor chip packaging structure and a packaging method thereof, comprising: a semiconductor chip, one side of which is provided with a functional area; a protective substrate covering the side of the semiconductor chip with a functional area; a supporting structure located between the semiconductor chip and the Between the protective substrates, the support structure includes a plurality of support arms connected end to end, the support arms surround the semiconductor chip and the protective substrate to form a sealed cavity, and the functional area is located in the sealed cavity Inside; at least one support arm has at least one supporting convex dam extending toward the direction of the functional area. The present invention sets the supporting convex dam so that the water vapor generates a vortex in the corner area of ​​the supporting convex dam, and the collision between the vortex and the water vapor occurs Friction produces energy loss, which reduces the impact of water vapor on the support structure, thereby effectively solving the problem of delamination and cracking of the support structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to the packaging technology of semiconductor chips. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) is a technology that packages the entire wafer and then cuts it to obtain a single finished chip. Wafer-level chip-scale packaging technology complies with the market's increasingly light, small, short, thin and low-cost requirements for microelectronic products. The size of the chip after dicing is almost the same as the size of the die, and the packaging cost is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a hot spot in the current packaging field and a future development trend. A single finished chip obtained by packaging and cutting needs to be tested for reliability, and only finished chips that pass the reliability test can be identified as qualified chi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/146
CPCH01L27/14618H01L27/1469
Inventor 段珍珍王宥军王鑫琴
Owner CHINA WAFER LEVEL CSP
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