Multi-rate decoder for binary QC-LDPC codes and decoding method thereof

Abstract

The invention discloses a multi-rate decoder for binary QC-LDPC codes based on configurable computation array architecture and a decoding method thereof. The decoder comprises a main controller, a main body decoding arithmetic unit, a data storage unit and a data transmission path; the main controller is used for receiving a decoding request and extracting decoding rate information; and the main body decoding arithmetic unit comprises a configurable computing unit array, an array configuration control logic unit and a configuration storage unit, wherein the configuration storage unit is used for storing the decoding rate and corresponding storage configuration information, the array configuration control logic unit is used for reading and analyzing the configuration information, and the configurable computing unit array is used for reconstructing the configuration according to the analyzed configuration information to achieve the decoding with the corresponding decoding rate. According to the multi-rate decoder, the configuration computing unit array with multiple functions can be subjected to function configuration via the array configuration control logic unit, and thereby different computing requirements under different decoding environments can be met.

Description

Technical field [0001] The invention relates to the design technology of a communication signal processor, in particular to a multi-rate binary QC-LDPC code decoder and decoding method based on a configurable computing array architecture. Background technique [0002] With the advent of the Internet era and the Internet of Things era, people's requirements for wireless communication technology are increasing. Compared with the previous communication technology, the current communication technology requires more and more key technical indicators such as bit error rate and throughput rate. high. [0003] The most important point in communication is to ensure the accuracy of the information and to communicate the information effectively and in a timely manner. Therefore, the two major characteristics that a communication system needs to have are low latency and low bit error rate. However, the relationship between the two is contradictory. Low latency requires the system to process ...

AI Technical Summary

Problems solved by technology

In the research of LDPC decoders, parallel architecture has gradually become the mainstream of research. With the continuous development of SDR, decoders based on traditional architectures such as ASIC cannot adapt to the rapidly changing decoding algorithms and the requirements of multi-standard compatibility. , the serial computing architecture is gradually replaced by the parallel architecture. As a configurable parallel architecture, the reconfigurable architecture caters to the development trend and demand of higher performance and higher flexibility of the decoder, and becomes a new research hotspot.

In the design, due to the use of uniform bit width, complex on-chip interconnection, and unoptimized algorithm mapping process, the use efficiency of hardware resources such as computing and storage resources is low.

Images