Automated testing method for fpga local interconnect resource based on reconfigurable unit

A technology of automated testing and partial interconnection, applied in error detection/correction, faulty computer hardware, instrument detection, etc., can solve problems such as increased complexity, reduce wiring requirements, reduce configuration generation difficulty, and high fault coverage rate effect

Active Publication Date: 2019-05-03
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the increasing scale of FPGA, local interconnect resources usually contain millions of interconnect segments and switches, resulting in a sharp increase in the complexity of the method

Method used

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  • Automated testing method for fpga local interconnect resource based on reconfigurable unit
  • Automated testing method for fpga local interconnect resource based on reconfigurable unit
  • Automated testing method for fpga local interconnect resource based on reconfigurable unit

Examples

Experimental program
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Effect test

Embodiment Construction

[0035] There are many ways to repeat the construction of the configuration unit, and the configuration methods are as follows:

[0036] For the repeated configuration unit composed of CLB and local interconnection, the lookup table in CLB is divided into Figure 4 Configured in the manner shown 8 , specifically, configure the adjacent eight LUTs into a specific operation form, and all input signals are connected to the input terminals of the first four LUTs. For the last four LUTs, one of the input signals comes from a specific front-end LUT. output (for example, an input of the fifth LUT comes from the output of the first LUT, an input of the sixth LUT comes from the output of the second LUT, and so on), other input signals are connected to the first four LUT inputs The signals are exactly the same. The result of logical operation among them ensures that the output signal is completely consistent with the input signal. For other input terminals in CLB, such as enable input...

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PUM

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Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an automatic testing method for FPGA local interconnection resources on the basis of repeatable configuration units. The method comprises the step of testing on all local interconnection line segments and all local programmable interconnection switches in an FPGA chip. According to the method, the regularity of an FPGA is fully utilized,the FPGA is subjected to local interconnection and configured to repeatable configuration unit templates with adjacent logic circuit resources, and then the unit templates are sequentially connected end to end and repeatedly traversed to the whole FPGA. Faults capable of being tested through the method comprise open circuits of the interconnection line segments, the short-circuit fault and the normally-opened and normally-closed faults of the interconnection switches. The method can complete testing on all the local interconnection resources in the FPGA chip and has higher applicability on FPGAs with different structures and scales. The configuration number, the configuration difficulty and the testing time needed by testing are all greatly optimized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a traversal test method for local interconnection resources in an FPGA (Field Programmable Gate Array). Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA), as a programmable logic device, not only solves the problems of long ASIC design cycle, high manufacturing cost and complex production process, but also avoids the problems of original programmable logic The disadvantages of limited number of device gates and low operating frequency. FPGA can be programmed through the hardware description language, the user uses the hardware description language to design the circuit, and then performs layout and wiring through the corresponding FPGA supporting software, generates a bit stream file and downloads it to the FPGA chip, so that the FPGA chip can be quickly configured to the user's needs circuit. [0003] Inte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
CPCG06F11/2215
Inventor 来金梅杨震王健杨萌
Owner FUDAN UNIV
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