Timing sequence netlist management method and device

A management method and a management device technology, which are applied in the field of timing netlist management methods and devices, and can solve the problems of large memory usage and large timing netlist contents, etc.

Active Publication Date: 2016-06-29
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present invention provides a timing netlist management method and device to solve the techni

Method used

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  • Timing sequence netlist management method and device
  • Timing sequence netlist management method and device
  • Timing sequence netlist management method and device

Examples

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no. 1 example

[0032] figure 1 It is a schematic structural diagram of the sequential netlist management device provided in the first embodiment of the present invention, which is composed of figure 1 It can be seen that in this embodiment, the timing netlist management device 1 provided by the present invention includes:

[0033] The modeling module 11 is used to obtain the timing netlist according to the design file, search the timing model of each device in the timing netlist, and establish a sub-timing netlist for each device; the sub-timing netlist includes all nodes of the device, each node and other nodes Connection relationship, the node includes the pin of the device;

[0034] The optimization module 12 is used to obtain the path delay information of the input node and its forward path in the sub-sequence netlist, add the path delay information of the forward path to the backward path of the input node, and delete the sub-sequence netlist Input nodes and their forward paths;

[0...

no. 2 example

[0041] figure 2 The flow chart of the sequential netlist management method provided by the second embodiment of the present invention is composed of figure 2 It can be seen that in this embodiment, the timing netlist management method provided by the present invention includes:

[0042] S201: Acquire the timing netlist according to the design file, search for the timing model of each device in the timing netlist, and establish a sub-timing netlist for each device; the sub-timing netlist includes all nodes of the device, the connection relationship between each node and other nodes, and the nodes include device pins;

[0043] S202: Obtain the path delay information of the input node and its forward path in the sub-sequence netlist, add the path delay information of the forward path to the backward path of the input node, delete the input node and its forward path in the sub-sequence netlist forward path;

[0044] S203: According to the port mapping relationship, a final ti...

no. 3 example

[0051] This example provides a timing netlist optimization method based on static timing analysis, which is used to optimize the storage structure of timing paths in the timing netlist, reduce memory usage, and improve the operating efficiency of EDA software while ensuring the accuracy of analysis results. This optimization method has two usages in timing analysis. One is to optimize the timing netlist of each device, and then connect each sub-timing netlist into the final netlist; the other is to directly optimize the final timing netlist. The netlist is optimized. The memory resources consumed by the two usages are the same, but the peak value of memory consumed by the second method will be higher than that of the first method. The code implementation of the first method is more complicated than the second method. Which one to use can be determined according to the situation. choose.

[0052] Such as image 3 As shown, the timing netlist management scheme provided by the ...

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Abstract

The invention provides a timing sequence netlist management method and device.The method comprises the steps of obtaining a timing sequence netlist according to a design document, searching for timing a sequence model of each set of equipment in the timing sequence netlist, and establishing a sub timing sequence netlist for each set of equipment, wherein each sub timing sequence netlist comprises all nodes of the corresponding equipment and connection relations of each node with other nodes, and each node comprises pins of the corresponding equipment; obtaining an input node of each sub timing sequence netlist and path time delay information of a forward path of the input node, adding the path time delay information of the forward path to a backward patch of the input node, and deleting the input node and the forward path of the input node in the corresponding sub timing sequence netlist; generating a final timing sequence netlist of the design document according to the port mapping relation and by means of the corresponding sub timing sequence netlist from which the input node and the forward path of the input node are deleted.By means of the timing sequence netlist optimization method based on static timing sequence analysis, the storage structure of the timing sequence paths in the timing sequence netlist is optimized, memory usage is reduced, accuracy of the analysis result is guaranteed, and EDA software operating efficiency is improved.

Description

technical field [0001] The invention relates to the field of FPGA timing analysis, in particular to a timing netlist management method and device. Background technique [0002] FPGA (Field-programmable Gate Array, Field Programmable Gate Array) is a product of further development on the basis of programmable devices. It appears as a semi-specified circuit in the field of ASIC (Application Specific Integrated Circuit, application specific integrated circuit), using FPGA The key advantage is that during the design phase the customer can modify the circuit as needed until they are satisfied with the design work. Static timing analysis is a very important aspect in large-scale integrated circuit design. In the circuit design process, in order to obtain an optimal circuit design, timing analysis plays a key role in structural logic, circuit layout and wiring. [0003] Static timing analysis not only checks the maximum delay of the circuit to ensure that the circuit can meet the ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/3312G06F2115/06
Inventor 王涛张敏
Owner SHENZHEN PANGO MICROSYST CO LTD
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