Nanowire array formation method

Abstract

The invention relates to a nanowire array formation method. The nanowire array formation method comprises steps that 1, the multi-period etching technology is carried out, and a multi-nanowire array is formed on a substrate; 2, annealing is carried out, and multiple nanowires are rounded; 3, a sacrificial layer is formed on the surface of the multiple nanowires; and 4, the sacrificial layer is removed, and multiple cylindrical nanowires are acquired. Through the method, after annealing and rounding processing on the nanowires, a reconstruction silicon layer on the surface is removed through sacrifice oxidation, so excellent-quality cylindrical nanowires are formed, nanowire array uniformity is improved, and performance and reliability of devices are improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a method for forming a nanowire array. Background technique [0002] With the continuous shrinking of integrated circuit devices according to the requirements of Moore's Law and the demand for more advanced devices in the consumer market, the current advanced logic CMOS device technology has reached the 22nm node and is expected to enter the 14 / 16nm node on time. This poses a challenge to many process technologies, especially etching technology, because it forms the pattern of the device, especially the lines of the active area, making the manufacture of integrated circuits possible. Among them, etching to form nanowires used as source and drain regions and channel regions is a key technology of CMOS VLSI. In addition, the nanowire transistor using the three-dimensional stacked "gate all around" nanowire channel has ultra-low static power co...

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Problems solved by technology

This method can precisely control the width of the nanowires through the etch selectivity between multiple overlapping layers, but the disadvantage is mainly that it is not compatible with the traditional IC process, because different layers of materials need to be deposited and additional different etching methods are used. Etching process (such as introducing other etching mechanisms than Si etching)

On the other hand, the cross-sectional shape of each nanowire in the nanowire array directly formed on the patterned silicon substrate by etching is usually a rhombus, because it is difficult to form a perfect arc in the isotropic etching process, Especially the rate of lateral erosion is difficult to control

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