Low-power-consumption comparator applied to pipelined ADC

Abstract

The invention discloses a low-power-consumption comparator applied to a pipelined ADC. The low-power-consumption comparator comprises a first-stage pre-amplification circuit, a second-stage amplification circuit and a latch circuit, wherein the first-stage pre-amplification circuit is composed of three PMOS pipes and two NMOS pipes, the tail current pipe and the load pipe of the first-stage pre-amplification circuit work under the control of a sampling clock, and the first-stage pre-amplification circuit outputs to the second-stage amplification circuit for further amplifying; the first-stage pre-amplification circuit opens when the falling edge of the sampling clock arrives, turns off when the falling edge of the sampling clock ends, completes latching before the maintenance phase arrives, and completes comparison operation by using the non-overlapped time of the two phases; and the second-stage amplification circuit resets the latch circuit when sampling, and further amplifies the output signal of the first-stage pre-amplification circuit and sends the amplified signal to the latch circuit. Compared with the traditional comparator, the comparator provided by the invention has the advantage of low zero static power consumption.

Description

technical field [0001] The invention relates to a low power consumption comparator applied to pipeline ADC. Background technique [0002] With the increasing popularity of portable device applications, low power consumption and high speed have become the two mainstream directions of ADC design. In the design of pipeline ADC, the design of relatively moderate input offset voltage low-power comparator is very important, which is related to the speed, accuracy, power consumption and chip area of ​​the entire ADC. To reduce the input offset voltage, it is often in the lock There is a pre-amplifier before the register, but the pre-amplifier often consumes a certain amount of static power consumption, so in order to design a low-power comparator, it is often necessary to reduce the static power consumption of the pre-amplifier. The working speed of the comparator also affects the working speed of the entire ADC. The result of the comparator determines the connection relationship ...

AI Technical Summary

Problems solved by technology

In the pipelined ADC design, the design of a low-power comparator with relatively moderate input offset voltage is very important, which is related to the speed, accuracy, power consumption and chip area of ​​the entire ADC. To reduce the input offset voltage, it is often in the lock There is a pre-amplifier before the register, but the pre-amplifier often consumes a certain amount of static power, so in order to design a low-power comparator, it is often necessary to reduce the static power consumption of the pre-amplifier

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