High-performance multi-port DDR (double data rate) controller and method for implementing same

A controller and high-performance technology, which is applied in the field of data communication, can solve the problems of DDR controllers having only one user port, waste of pins and logic resources, etc., to ensure bandwidth utilization, save pin resources and logic resources, and simplify The effect of design difficulty

Active Publication Date: 2016-08-17
烽火超微信息科技有限公司
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Problems solved by technology

[0004] In the general FPGA-based DDR controller design, capacity and bandwidth can be increased by superimposing DDR memories. The disadvantage is that a DDR controller has onl

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  • High-performance multi-port DDR (double data rate) controller and method for implementing same
  • High-performance multi-port DDR (double data rate) controller and method for implementing same

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Embodiment Construction

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0039] In order to meet the needs of multiple users accessing the same DDR interface at the same time, in addition to providing users with an easy-to-use interface, it supports users to read and write on the local bus or transfer large blocks of data similar to DMA (Directional Memory Access, direct memory access); At the same time, it is necessary to reasonably allocate the bandwidth of the DDR interface (only for the user interface in the working state to evenly allocate bandwidth), so as to improve the bandwidth utilization.

[0040] see figure 1 As shown, the embodiment of the present invention provides a high-performance multi-port DDR controller, the controller includes a local bus and read and write message conversion module, a user interface and a read and write message conversion module, and a read / write message downlink arbi...

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Abstract

The invention discloses a high-performance multi-port DDR (double data rate) controller and a method for implementing the same, and relates to the field of data communication. The high-performance multi-port DDR controller comprises local bus, a read-write message conversion module, user interface and read-write message conversion modules, a read/write message downstream arbitration module, a read reply data message upstream port selection module, a read-write message and DDR interface conversion module and a DDR interface module. The high-performance multi-port DDR controller and the method have the advantages that an architecture with a DDR interface shared by multiple user ports is economical and flexible, accordingly, pin resources and logical resources can be saved to a great extent, and the design difficulty can be lowered.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a high-performance multi-port DDR controller and its realization method. Background technique [0002] With the continuous development of IP (Internet Protocol, Internet Protocol)-based transmission networks, the network protocol functions based on FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chips have more and more demands for large-capacity, high-speed data caches. more urgent. The traditional data caching scheme is realized based on FPGA on-chip block RAM (block random access memory). This solution has the advantages of high speed, flexible configuration, and convenient use, but the disadvantages of high cost and small capacity make it less and less suitable for the protocol data cache with a large number of entries. [0003] DDR (Double Data Rate, double-rate synchronous dynamic random access memory) was released by JEDEC (Joint Electronic Device En...

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Application Information

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IPC IPC(8): G06F13/16G06F13/18
CPCG06F13/1605G06F13/1678G06F13/18
Inventor 韩震
Owner 烽火超微信息科技有限公司
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