High-performance multi-port DDR (double data rate) controller and method for implementing same

Abstract

The invention discloses a high-performance multi-port DDR (double data rate) controller and a method for implementing the same, and relates to the field of data communication. The high-performance multi-port DDR controller comprises local bus, a read-write message conversion module, user interface and read-write message conversion modules, a read / write message downstream arbitration module, a read reply data message upstream port selection module, a read-write message and DDR interface conversion module and a DDR interface module. The high-performance multi-port DDR controller and the method have the advantages that an architecture with a DDR interface shared by multiple user ports is economical and flexible, accordingly, pin resources and logical resources can be saved to a great extent, and the design difficulty can be lowered.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a high-performance multi-port DDR controller and its realization method. Background technique [0002] With the continuous development of IP (Internet Protocol, Internet Protocol)-based transmission networks, the network protocol functions based on FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chips have more and more demands for large-capacity, high-speed data caches. more urgent. The traditional data caching scheme is realized based on FPGA on-chip block RAM (block random access memory). This solution has the advantages of high speed, flexible configuration, and convenient use, but the disadvantages of high cost and small capacity make it less and less suitable for the protocol data cache with a large number of entries. [0003] DDR (Double Data Rate, double-rate synchronous dynamic random access memory) was released by JEDEC (Joint Electronic Device En...

AI Technical Summary

Problems solved by technology

[0004] In the general FPGA-based DDR controller design, capacity and bandwidth can be increased by superimposing DDR memories. The disadvantage is that a DDR controller has only one user interface.

For multi-user application scenarios, it is necessary to instantiate a DDR controller for each user, which is a great waste of FPGA pins and logic resources

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