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A PCB design method for an embedded system based on an A20

An embedded system and design method technology, applied in computing, special data processing applications, instruments, etc., can solve the problem of high manufacturing cost, and achieve the effect of reducing the number of PCB layers, ensuring stability, and reducing design and manufacturing costs

Active Publication Date: 2016-08-17
AEROSPACE HI TECH HLDG GROUP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problem of relatively high manufacturing cost when manufacturing smaller-sized PCBs according to existing PCB design methods

Method used

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  • A PCB design method for an embedded system based on an A20
  • A PCB design method for an embedded system based on an A20
  • A PCB design method for an embedded system based on an A20

Examples

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specific Embodiment approach 1

[0015] 1, a kind of PCB design method based on the embedded system of A20, it is characterized in that concrete design method is as follows:

[0016] Design an embedded system based on A20, which mainly includes core controller A20, DDR3 (high-speed data cache), NAND Flash (mass data storage), clock chip and power module;

[0017] Such as figure 1 As shown, in the overall layout of the board, since DDR3 and NAND FLASH have many high-speed signal lines, DDR3 and NAND FLASH are respectively designed on the upper and lower sides or left and right sides of the core controller A20, and the Wiring is given priority; the power module and the clock chip are arranged on the left and right sides or the top and bottom sides of the core controller A20 respectively, and the clock chip is designed to be close to the core controller A20;

[0018] The PCB stackup design of the A20-based embedded system is 8 layers, including 5 wiring layers, 2 GND layers and 1 power layer.

[0019] image ...

specific Embodiment approach 2

[0020] The PCB laminate described in this embodiment is designed according to the following principles:

[0021] In terms of PCB stacking, priority is given to ensuring that the high-speed signal (above 100MHz) line has a complete reference ground plane, and the power signal is processed through the power plane as much as possible to ensure sufficient flow capacity. For low-speed signals (below 10MHz) or level signals, adjacent Layer routing to reduce the number of PCB layers and reduce costs.

[0022] Other steps and parameters are the same as those in Embodiment 1.

specific Embodiment approach 3

[0023] The specific design method of the PCB laminate described in this embodiment is as follows:

[0024] The PCB stack design is 8 layers, from top to bottom are TOP layer, GND layer, L3 layer, L4 layer, POWER layer, L6 layer, GND layer, BOTTOM layer;

[0025] DDR3 data lines and address lines have the highest rate, up to 1Gsps. Therefore, DDR3 is regarded as a single block in layout, and DDR3 is far away from NAND Flash, clock chip and power module design in plane layout, that is, DDR3 and NAND are combined in plane layout. The design of maximizing the distance between the Flash, the clock chip and the power module is to make the space as far as possible, and the ultimate goal is to ensure that the distance between the two signal lines is greater than 5 times the width of the PCB trace;

[0026] Prioritize the design of DDR3 wiring on the L3, L6, TOP, and BOTTOM layers, design the wiring length as short as possible, and the line spacing as large as possible; all data lines,...

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Abstract

The invention provides a PCB design method for an embedded system based on an A20 and relates to a PCB design method. The invention aims to solve the problem that the manufacture cost of a PCB with a smaller size is relatively high when the PCB is manufactured according to the conventional PCB design method. An A20-based embedded system is designed; the system mainly comprises a central controller A20, a DDR3, an NAND flash, a clock chip and a power module; in the overall planar layout of a single board, the DDR3 and the NAND flash are arranged on the upper and lower sides or the left and right sides of the central controller A20 and wiring is performed preferentially for the same; the power module and the clock chip are arranged on the left and right sides or the upper and lower sides of the central controller A20; the clock chip is designed to be pressed against the central controller A20; the PCB stackup of the A20-based embedded system has 8 layers, including 5 wiring layers, 2 GND layers and 1 power source layer. The method is applied to the field of PCB design.

Description

technical field [0001] The invention relates to a PCB design method. Background technique [0002] With the continuous development of the electronics industry, more and more embedded systems controlled by ARM are used in the field of automotive electronics, such as car navigation, audio-visual entertainment and other equipment. In order to achieve a better user experience, the running speed of the embedded system is faster The requirements for performance and stability are getting higher and higher, but the design and manufacturing costs of its PCB are also getting higher and higher. In view of the strict requirements of the automotive electronics industry on system stability and cost, in order to ensure performance Under the premise, the need to reduce the design and manufacturing costs of high-speed embedded system PCBs has become increasingly prominent. [0003] The PCB of a high-speed embedded system is usually a multi-layer board, and the higher the system performance ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 鄂鸿飞吕端秋仇骁
Owner AEROSPACE HI TECH HLDG GROUP
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