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Sub-threshold to super-threshold cmos level-shifting circuit against single event effect

An anti-single event effect and ultra-threshold technology, applied in logic circuits, electrical components, reliability improvement and modification, etc., can solve problems such as faults and system errors, and achieve the effects of reliable circuit operation, avoiding flipping, and low cost

Active Publication Date: 2018-11-09
HOHAI UNIV CHANGZHOU
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This effect, known as a single event effect (SEE), can cause system errors, causing serious malfunctions

Method used

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  • Sub-threshold to super-threshold cmos level-shifting circuit against single event effect
  • Sub-threshold to super-threshold cmos level-shifting circuit against single event effect

Examples

Experimental program
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Embodiment

[0023] Such as figure 1 , in this embodiment, the inverting unit includes a PMOS transistor MP 1 and an NMOS tube MN 1 , MP 1 The source is connected to the power supply, and the drain is connected to the MN 1 The drain, and as the signal output terminal V of the inverting unit sub_b ; MN 1 The source of the ground; MP 1 The gate and MN 1 The gate is connected and used as the signal input terminal V of the inverting unit sub .

[0024] Such as figure 2 , the level conversion unit from sub-threshold to super-threshold with anti-single event effect consists of 4 PMOS transistors MP X1 , MP X2 , MP X3 , MP X4 , and 8 NMOS tubes MN X1 , MN X2 , MN X3 , MN X4 , MN X5 , MN X6 , MN X7 , MN X8 Composition, where MP X1 , MP X2 , MP X3 , MP X4 and MN X1 , MN X2 , MN X3 , MN X4 constitutes the level conversion module, MP X1 , MP X2 , MP X3 , MP X4 and MN X5 , MN X6 , MN X7 , MN X8 Constitute the anti-single event effect module.

[0025] MP X1 , MP ...

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Abstract

The invention discloses a subthreshold-to-super-threshold CMOS (Complementary Metal Oxide Semiconductor) level conversion circuit capable of resisting a single event effect. The subthreshold-to-super-threshold CMOS level conversion circuit comprises a phase-inverting unit and a subthreshold-to-super-threshold level conversion unit capable of resisting the single event effect, wherein the phase-inverting unit comprises a signal input end and a signal output end; a phase of a signal output by the signal output end is inverse to a phase of a signal input by the signal input end; and the subthreshold-to-super-threshold level conversion unit capable of resisting the single event effect comprises four PMOS (P-channel Metal Oxide Semiconductor) transistors, four NMOS (N-channel Metal Oxide Semiconductor) transistors capable of constructing a level conversion module together with the four PMOS transistors, and four NMOS transistors capable of constructing a single event effect resisting module together with the four PMOS transistors. An initial signal of a subthreshold is inverted into an inversion signal through a phase inverter; the initial signal and the inversion signal of the initial signal are taken as inputs; subthreshold-to-super-threshold level conversion can be realized through the level conversion unit; and an effect of resisting the single event effect is achieved. The subthreshold-to-super-threshold CMOS level conversion circuit can be obtained through modification of a conventional level converter in order to prevent output errors caused by the single event effect.

Description

technical field [0001] The invention relates to the technical field of single-event effect suppression, in particular to a CMOS level conversion circuit from sub-threshold to super-threshold against single-event effect. Background technique [0002] In order to reduce the power consumption of electronic systems, the operating voltage of many chips has become lower and lower. For example, processor I / O voltages are being reduced from 1.8V to 1.5V, while cores can operate at voltages below 1V. Even, there are various voltage domains in the core of the processor. The uneven progress in voltage reduction presents a critical challenge that system designers must address—how to reliably transition between signal levels. [0003] Some chips can convert from a higher logic level to a lower logic level, and some chips can convert a lower logic level to a higher logic level. When these logic conversion chips are applied in the space environment, space radiation high-energy particles...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/003
CPCH03K19/00338
Inventor 王海滨戴茜茜张学武李庆武刘小锋孙洪文华迪
Owner HOHAI UNIV CHANGZHOU
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