A method of resisting power consumption attack based on random delay for des algorithm
A random delay and anti-power consumption technology, applied in encryption devices with shift registers/memory, digital transmission systems, secure communication devices, etc., can solve the problem of weakening the correlation between Hamming weight and power consumption of intermediate result data Completely resist power consumption attacks, high hardware resource overhead, etc., to achieve the effect of low hardware resource overhead, low performance overhead, and resistance to power consumption attacks
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0020] The technical solution of the present invention will be further introduced below in combination with specific embodiments.
[0021] The traditional DES algorithm consists of three parts, such as figure 1 Shown are the initial permutation, 16 rounds of the same round operation, and the inverse initial permutation transformation. Each round requires a round key to complete the key addition operation, and there are a total of sixteen subkeys, denoted as Kn (n=0,...,16). The subkey is obtained from the initial key through initial permutation, left circular shift and permutation selection. The 16-cycle round operation in the middle of the DES algorithm includes five operations: extension, XOR operation, byte replacement, permutation, and XOR operation. At the end of each round of DES, two 32-bit intermediate value data will be generated, which can be recorded as Ln (n=0,...,16), and Rn (n=0,...,16) are stored in registers L and R, where L 16 and R 16 Combined into a 64-b...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


