Chip package technology and chip package structure

Abstract

The present invention provides a chip package technology and a chip package structure. After a chip is packaged to a package carrier, the position information of an electrode pad on the chip is obtained, the cover body of the chip is covered, and the position information of the electrode pad is obtained; and the cover body is subjected to opening processing to bare the electrode terminal of the chip, and finally the electrode terminal is electrically connected with an external circuit. The package technology is simple, and the package structure formed by the technology is low in manufacturing cost and high in reliability and integration level.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip packaging process and a chip packaging structure. Background technique [0002] In the manufacture of integrated circuits, chips are typically packaged prior to integration with other electronic assemblies. The chip packaging process that was widely used in the early days was the wire bonding packaging process, that is, the electrode terminals on the chip are bonded to the lead frame through metal wires, and then the packaging method is plastic-encapsulated. However, the area of ​​the packaging structure formed by the wire bonding packaging process is relatively large, and the packaging performance cannot be effectively improved due to the influence of metal lead resistance and parasitic capacitance. Therefore, the flip-chip packaging process emerged as the times require, and the flip-chip packaging structure formed by the flip-chip packaging process has attracted ...

AI Technical Summary

Problems solved by technology

However, if figure 2 As shown, part of the chip 02 cannot be pasted to the predetermined position on the package substrate 00 (the dotted line) very precisely. This inevitable deviation during pasting will cause the chip 02 to be buckled upside down on the lead frame 01, as shown in Figure 4 As shown, the conductive bump 021 cannot be electrically connected to the corresponding pad on the lead frame, which may cause a short circuit or open circuit of the package structure, which affects the reliability of the package.

[0004] In addition, in the above-mentioned flip-chip packaging process, since the chip 02 is electrically connected to the lead frame 01 and then plastic-encapsulated, when the size of the conductive bump 021 is small, it is difficult to fill the plastic compound between the chip 02 and the lead frame 01 In the gap between, it is necessary to adopt the underfill process with high process difficulty, which increases the process difficulty and manufacturing cost

Moreover, since the chip 02 and the lead frame 01 need to use conductive bumps to realize the electrical connection, however, since the conductive bumps on the active surface of the chip 02 have a certain size (usually larger than the size of the pad), when the chip is active When the number of electrode terminals on the surface increases, the distance between the pads of these electrode terminals and the pads will become smaller and smaller, so that it is impossible to make solder balls or conductive bumps on the pads to realize the connection with the external circuit. electrical connection

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