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Method for fabricating semiconductor component

A technology for semiconductors and components, applied in the field of manufacturing semiconductor components, can solve problems such as affecting the electrical performance of components and the loss of epitaxial layers.

Inactive Publication Date: 2016-10-05
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, in the existing fin field effect transistor manufacturing process, the epitaxial layer is often corroded and worn out by chemical solutions during various cleaning processes, which in turn affects the overall electrical performance of the device

Method used

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  • Method for fabricating semiconductor component
  • Method for fabricating semiconductor component
  • Method for fabricating semiconductor component

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Embodiment Construction

[0020] Please refer to Figure 1 to Figure 8 , Figure 1 to Figure 8 It is a schematic diagram of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention, which can be implemented in the manufacturing process of planar or non-planar transistor devices, and is now applied to the manufacturing process of non-planar transistor devices as an example. Such as figure 1 As shown, firstly, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which a transistor region, such as a PMOS transistor region or an NMOS transistor region, is defined. There is at least one fin structure 14 and an insulating layer on the substrate 12, wherein the bottom of the fin structure 14 is covered by an insulating layer, such as silicon oxide, to form a shallow trench isolation 16, and part of the fin structure 14 is also provided with There are a plurality of gate structures 18 , 20 , 22 .

[0021] T...

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Abstract

The invention discloses a method for fabricating a semiconductor component. The method includes the following steps that: a substrate is provided, wherein the substrate is provided with a gate structure which is arranged on the substrate and an interlayer dielectric layer which surrounds the gate structure; a dielectric layer is formed on the gate structure and the interlayer dielectric layer; a patternized hard mask is formed on the dielectric layer; an opening is formed in the dielectric layer and the interlayer dielectric layer; a silicified metal production process is carried out to form a silicified metal layer in the opening; after the silicified metal production process, the patternized hard mask and unreacted metal are removed; and a contact plug is formed in the opening.

Description

technical field [0001] The invention relates to a method for manufacturing semiconductor elements, in particular to a method for simultaneously removing a patterned mask made of titanium nitride and unreacted metal in the metal silicide manufacturing process after the metal silicide manufacturing process. Background technique [0002] In recent years, as the size of field effect transistors (FETs) continues to shrink, the development of existing planar field effect transistors is facing the limit of the manufacturing process. In order to overcome manufacturing process limitations, it has become a mainstream development trend to replace planar transistor devices with non-planar field effect transistor devices, such as fin field effect transistor (Fin FET) devices. Since the three-dimensional structure of the fin field effect transistor element can increase the contact area between the gate and the fin structure, it can further increase the control of the gate on the carrier c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/768
CPCH01L29/785H01L29/41791H01L29/66545H01L29/66795H01L21/28518H01L21/324H01L21/3081H01L21/28052H01L21/32053H01L29/665
Inventor 洪庆文吴家荣黄志森陈意维许家彰
Owner UNITED MICROELECTRONICS CORP