Sealing ring of chip

A sealing ring and chip technology, which is applied to electrical components, electric solid devices, circuits, etc., can solve the problem of chip edge delamination, and achieve the effect of preventing chip edge delamination and increasing deformation capacity

Active Publication Date: 2016-10-05
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of this application is to provide a chip sealing ring to solve the problem of easy delamination of the edge of the chip in the scribing process of the prior art

Method used

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Embodiment Construction

[0038] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0039] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, it indicates There are features, steps, operations, means, components and / or combinations thereof.

[0040] For the convenience of description, spatially relative terms may be used here...

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Abstract

The application provides a chip sealing ring. The sealing ring includes one or more sealing units, each sealing unit includes: a first metal wiring layer arranged around the chip, the first metal wiring layer includes a first metal part and a first dielectric material part isolated from each other; a second metal wiring Layer, set opposite to the first metal wiring layer, the second metal wiring layer includes a second metal part and a second dielectric material part isolated from each other; an interlayer dielectric layer, set between the first metal wiring layer and the second metal wiring layer Between: one or more via hole groups, disposed in the interlayer dielectric layer around the chip and connecting the first metal part and the second metal part, the via hole group includes a plurality of via holes independent of each other. The mechanical stress formed by the via hole breaks through the barrier of the adhesion between the first metal part and the second metal part and the via hole, which alleviates the problem of chip edge delamination; on the other hand, the rigidity of the via hole decreases, resulting in an increase in deformation capacity. Therefore, the occurrence of chip edge delamination is effectively prevented.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular, to a sealing ring of a chip. Background technique [0002] In a semiconductor manufacturing process, a semiconductor chip including a semiconductor active device and an interconnection structure disposed on the device can be formed on a semiconductor substrate through processes such as photolithography, etching, and deposition. Usually, multiple chips can be formed on a wafer, and finally these chips are cut off from the wafer for packaging process to form an integrated circuit area. During the process of dicing the chip, the stress generated by the dicing knife will cause damage to the edge of the chip, and even cause the chip to collapse. In the prior art, in order to prevent the chip from being damaged during dicing, a sealing ring is provided around the active device area of ​​the chip, which can block the stress generated by the dicing knife and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L23/02
Inventor 张贺丰侯大维
Owner SEMICON MFG INT (SHANGHAI) CORP
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