The invention provides a sealing ring of a
chip. The sealing ring comprises one or more sealing units; each sealing unit comprises a first
metal wiring layer, a second
metal wiring layer, an interlayer
dielectric layer, and one or more via hole groups; the first
metal wiring layer surrounds the
chip; the first metal wiring layer includes a first metal portion and a first
dielectric material portion which are insulated from each other; the second metal wiring layer is opposite to the first metal wiring layer; the second metal wiring layer includes a second metal portion and a second
dielectric material portion which are insulated from each other; the interlayer
dielectric layer is arranged between the first metal wiring layer and the second metal wiring layer; the one or more via hole groups surround the
chip, are arranged in the interlayer
dielectric layer and are connected with the first metal portion and the second metal portion; and each via hole group includes a plurality of via holes which are independent from each other. A via hole formation mechanical stress breaks through the obstruction of an
adhesion force between the first metal portion, the second metal portion and the via holes, so that the problem of
delamination of the edge of the chip can be alleviated; and the rigidness of the via holes is decreased, so that the deformation ability of the via holes can be increased, and therefore, the
delamination of the edge of the chip can be effectively prevented.