A data clock recovery circuit and its phase interpolator
A phase interpolator and recovery circuit technology, applied in electrical components, pulse technology, pulse processing, etc., can solve problems such as poor dynamic performance of data clock recovery circuits
Active Publication Date: 2018-10-23
LONTIUM SEMICON CORP
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Problems solved by technology
[0004] In view of this, the present invention provides a data clock recovery circuit and its phase interpolator to solve the problem of poor dynamic performance of the data clock recovery circuit in the prior art
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[0070] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
[0071] The present invention provides a phase interpolator of a data clock recovery circuit to solve the problem of poor dynamic performance of the data clock recovery circuit in the prior art.
[0072] Specific, such as figure 1 As shown, the phase interpolator of the data clock recovery circuit is connected to the control unit of the data clock recovery circuit, and the phase interpolator includes:
[0073] An encoding circuit 101 with an ...
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The phase interpolator of the data clock recovery circuit disclosed in the present invention generates and outputs the first code and the second code through the coding circuit according to the control of the control unit of the data clock recovery circuit; received by the multiplexer and according to the second Encoding, selecting two of the received N phase clocks for output; receiving by the clock mixer and according to the first encoding, receiving and outputting a new phase clock generated and output after receiving the two phase clocks for weighted analog operation; Then the small signal output by the clock mixer is amplified into a full-swing signal by a differential-to-single-ended amplifier, and supplied to the control unit to judge whether the data sampled by the clock at the current position is the best sampled data, if not The encoding circuit is further controlled to change the delay position of the output clock of the phase interpolator to make the clock advance or lag, and finally a stable state in which the clock dynamically follows the data is formed.
Description
Technical field [0001] The present invention relates to the technical field of data clock recovery, in particular to a data clock recovery circuit and its phase interpolator. Background technique [0002] In the receiving end of the serial communication system, the data clock recovery circuit (CDR, Clock and Data Recovery) is used to extract the clock from the received serial data stream and recover the data. The performance of the CDR directly restricts the quality of communication. The phase interpolator (PI, Phase Interpolator) is used to adjust the sampling clock phase in the CDR, so as to realize the correct sampling of the data. The PI that can accurately adjust the clock phase is very important for the receiving end to be able to correctly recover the data at the transmitting end. [0003] In practical applications, due to the influence of process and ambient temperature, a phase step may occur during the working process of the CDR, which leads to a decline in its jitter pe...
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IPC IPC(8): H03K5/135
Inventor 邰连梁夏洪锋沈勇张志存陈晓飞刘志明陈峰
Owner LONTIUM SEMICON CORP