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Time-interleaved analog-to-digital converter

A time interleaving and converter technology, applied in the direction of analog-to-digital converter, code conversion, analog-to-digital conversion, etc., can solve problems such as SN ratio deterioration, and achieve the effect of timing offset correction and reduction of timing offset.

Inactive Publication Date: 2016-11-16
PANASONIC INTPROP MANAGEMENT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In particular, when a high-frequency signal is input, the AD conversion error caused by the timing offset is largely exhibited, and the SN ratio is greatly deteriorated

Method used

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Embodiment Construction

[0034] (recognition that is the basis of this application)

[0035] First, knowledge that is the basis of this application will be described. In the conventional timing offset correction method, when the speed of the AD converter is increased and the resolution is increased, it is necessary to divide the phase control steps of the DAC output into finer steps, which leads to an increase in the correction time and an increase in the correction time. The complication of the additional circuit. In addition, it is difficult to generate reference signals such as ramp waves as the speed and resolution of AD converters increase.

[0036] Therefore, the inventors of the present invention have made intensive studies in order to realize a time-interleaved AD converter capable of correcting the timing offset accurately and preventing the occurrence of AD conversion errors while suppressing the scale of the additional circuit for correction.

[0037] A technical solution of the present a...

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Abstract

A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1 / N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N1) variable delay circuit that adjusts delay time for at least (N1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Description

technical field [0001] The present invention relates to a time-interleaved AD converter. Background technique [0002] There are various architectures for AD converters, and they are used according to specifications such as resolution, sampling frequency, and power consumption. Among them, since it is difficult to realize an AD converter operating at a high-speed sampling frequency exceeding 1 GHz with a single AD converter, a time-interleaved (interleaved) type AD converter is often used. [0003] A time-staggered AD converter has a structure in which N (N is an integer greater than 2) AD converters (hereinafter referred to as "channel AD converters") are arranged, and an operation clock whose phase is equally shifted is input to each AD converter. signal, after AD conversion, each output data is combined. Therefore, the operating clock frequency of the AD converter of each channel can be set to 1 / N times the sampling frequency. As a result, it can also be realized with ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12H03M1/06
CPCH03M1/0626H03M1/1215H03M1/1061H03M1/0836
Inventor 三木拓司中顺一尾关俊明
Owner PANASONIC INTPROP MANAGEMENT CO LTD
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