Sampling circuit for sampling signal input and related control method

Abstract

A sampling circuit (100, 400) for sampling a signal input is provided. The sampling circuit (100, 400) includes a signal generation circuit (110, 510), a sampling switch (M SS , M SS1 , M SS2 , M SS3 , M SS4 ) and a control circuit (120, 220, 320, 420, 720). The signal generation circuit (110, 510) is arranged for generating a first control signal. The sampling switch (M SS , M SS1 , M SS2 , M SS3 , M SS4 ) has a control node (N CTS , N C1 , N C2 , N C3 , N C4 ), and is arranged for determining a sampling time of the signal input according to a signal level at the control node (N CTS , N C1 , N C2 , N C3 , N C4 ). The control circuit (120, 220, 320, 420, 720) is arranged for controlling the signal level at the control node (N CTS , N C1 , N C2 , N C3 , N C4 ), wherein when the signal level at the control node (N CTS , N C1 , N C2 , N C3 , N C4 ) corresponds to a first level, and before a signal level of the first control signal is changed in order to adjust the signal level at the control node (N CTS , N C1 , N C2 , N C3 , N C4 ) to a second level, the control circuit (120, 220, 320, 420, 720) couples the first control signal to the control node (N CTS , N C1 , N C2 , N C3 , N C4 ).

Description

technical field [0001] Embodiments of the present invention relate to the technical field of signal sampling, and in particular, relate to a sampling circuit for sampling an input signal and a control method thereof, which can reduce mismatch sources between channels. Background technique [0002] Traditionally, a time-interleaved architecture is used to implement a high-speed and high-resolution analog-to-digital converter (analog-to-digital converter; ADC, hereinafter referred to as ADC for analog-to-digital converter). However, offset errors, gain errors, and timing skew can degrade the performance of time-interleaved ADCs. Reducing timing skew is more difficult than offset and gain errors. Although the time required to transmit the input signal to each signal path (channel) is the same, the devices between the signal paths can cause mismatches due to process constraints, where mismatched devices are the source of the mismatch. [0003] Currently, the traditional approa...

AI Technical Summary

Problems solved by technology

However, offset errors, gain errors, and timing skew can degrade the performance of time-interleaved ADCs

Reducing timing skew is more difficult than offset and gain errors

Although the time required to transmit the input signal to each signal path (lane) is the same, the devices between the signal paths can cause mismatch due to process constraints, where the mismatched device is the source of the mismatch

[0003] Currently, the traditional approach to reducing timing skew is to use master clock sampling techniques, but device mismatches still occur in the control logic for master clock sampling

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