Sampling circuit and control method for sampling input signal

Abstract

The invention provides a sampling circuit for sampling an input signal and a control method thereof. The sampling circuit includes a signal generating circuit, a sampling switch and a control circuit, the signal generating circuit generates a first control signal, the sampling switch has a control node, and is used to determine the sampling time of the input signal according to the signal level of the control node, and the control circuit controls the control node , wherein when the signal level of the control node corresponds to the first level, and before changing the signal level of the first control signal to adjust the signal level of the control node to the second level, the control circuit will The first control signal is coupled to the control node. The invention can reduce the mismatch sources between the various signal paths, and reduce the timing skew caused by the mismatch sources.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of signal sampling, and in particular, relate to a sampling circuit for sampling an input signal and a control method thereof, which can reduce mismatch sources between channels. Background technique [0002] Traditionally, a time-interleaved architecture is used to implement a high-speed and high-resolution analog-to-digital converter (analog-to-digital converter; ADC, hereinafter referred to as ADC for analog-to-digital converter). However, offset errors, gain errors, and timing skew can degrade the performance of time-interleaved ADCs. Reducing timing skew is more difficult than offset and gain errors. Although the time required to transmit the input signal to each signal path (channel) is the same, the devices between the signal paths can cause mismatches due to process constraints, where mismatched devices are the source of the mismatch. [0003] Currently, the traditional approa...

AI Technical Summary

Problems solved by technology

However, offset errors, gain errors, and timing skew can degrade the performance of time-interleaved ADCs

Reducing timing skew is more difficult than offset and gain errors

Although the time required to transmit the input signal to each signal path (lane) is the same, the devices between the signal paths can cause mismatch due to process constraints, where the mismatched device is the source of the mismatch

[0003] Currently, the traditional approach to reducing timing skew is to use master clock sampling techniques, but device mismatches still occur in the control logic for master clock sampling

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