Power-up/power-down reset circuit and chip

A technology of electric reset and circuit, which is applied in the field of circuits, can solve problems such as unstable circuit node voltage and logic state of circuit components, achieve the effects of reducing energy consumption, fewer branches, and improving reliability

Active Publication Date: 2016-12-07
ZHUHAI JIELI TECH
View PDF4 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Usually, when the power supply voltage of the circuit system has not reached the expected stable state at the initial stage of power-on, the voltage and logic state of many circuit components (mainly semiconductor devices) and circuit nodes are unstable.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Power-up/power-down reset circuit and chip
  • Power-up/power-down reset circuit and chip
  • Power-up/power-down reset circuit and chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] In order to make the object, technical solution and advantages of the present invention clearer, the specific implementation manners of the power-on and power-down reset circuit and the chip including the circuit of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0027] It should also be noted that in the power-on and power-down reset circuits of the following embodiments, NMOS transistors and PMOS transistors are involved, and the NMOS transistors and PMOS transistors have corresponding source S, drain D, and gate G respectively. However, due to the symmetrical structure of the NMOS transistor and the PMOS transistor, when the NMOS transistor and the PMOS transistor are connected, the connection positions of the source S and the drain D are substantially interchangeable. C...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a power-up / power-down reset circuit and a chip. The circuit comprises a starting resistance circuit, a PMOS tube M1, a PMOS tube M2, an NOMS tube M3 and an NMOS tube M4; the starting resistance circuit is connected between a power supply and the ground, and comprises a first resistance voltage-dividing module, a second resistance voltage-dividing module, a third resistance voltage-dividing module and a fourth resistance voltage-dividing module; a first metal pole of M1 and a first metal pole of M2 are respectively connected to the power supply; a second metal pole of M1 and a grid electrode of M2 are connected with a second metal pole of the first resistance voltage-dividing module; a grid electrode of M1 is connected with a second metal pole of the second resistance voltage-dividing module; a second metal pole of M2 is connected with a first metal pole of M3; a first metal pole of M3 is connected with a grid electrode of M3 and then connected with a grid electrode of M4; a first metal pole of M4 is connected with a second metal pole of the third resistance voltage-dividing module; and a second metal pole of the fourth resistance voltage-dividing module, a second metal pole of M3 and the second metal pole of the tube M4 are connected to the ground.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to a power-on and power-off reset circuit and a chip. Background technique [0002] The power-on and power-off reset signal is a crucial signal in sequential circuits such as microcontrollers, and is the key to whether sequential circuits and chips such as microcontrollers can operate normally. In traditional technology, a small number of electronic devices, chips, etc. are provided with reset signals by external dedicated power-on reset chips, and most of them have built-in power-on reset circuits to provide reset signals. [0003] Usually, when the power supply voltage of the circuit system has not reached the expected stable state at the initial stage of power-on, the voltage and logic state of many circuit components (mainly semiconductor devices) and circuit nodes are unstable. [0004] figure 1 and figure 2 Two common power-on reset circuits in conventional technology are...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F1/24
CPCG06F1/24
Inventor 陈伟舜
Owner ZHUHAI JIELI TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap