Digital Delay Unit And Signal Delay Circuit

Abstract

An example of the invention provides a digital delay unit that is made up of a plurality of NAND gates. The digital delay unit includes a first delay path and a second delay path. The first delay path is coupled between a first input terminal and an output terminal to provide a basic time delay which is caused by one NAND gate. The second delay path is coupled between a second input terminal and the output terminal to provide at least three basic time delays.

Description

technical field [0001] The present invention is a signal delay circuit, especially an all-digital signal delay circuit. Background technique [0002] With the advancement of semiconductor technology, the operating frequency of integrated circuits is getting faster and faster, and the out-of-synchronization between internal components and external components of integrated circuits is becoming more and more serious. In order to eliminate this asynchrony, it is necessary to design a phase-locked loop (PLL) or a delay-locked loop (DLL) inside the integrated circuit to correct the clock, so that all the internal circuits of the integrated circuit The clock phases of the components can all be the same. Generally speaking, the phase-locked loop includes a voltage controlled oscillator, and the voltage-controlled oscillator often has unavoidable cumulative jitter, which makes the noise immunity of the phase-locked loop low. in a delay locked loop. [0003] The delay locked loop i...

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Problems solved by technology

Similarly, in case the phase delay required by the clock signal CLKA or CLKB is less than 2T d or (T d +T), then Figure 1B The digital delay line in the

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