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Video image compressed sensing coder-decoder system and coding-decoding method thereof

A technology of compressed sensing and codec, which is applied in the field of video image compressed sensing codec system and its codec, which can solve the problem of difficult to achieve source and channel optimization codec, waste of data and system resources, complex coder, etc. problems, to avoid loss of image details, reduce complexity, and save hardware resources

Inactive Publication Date: 2016-12-07
GUANGDONG POLYTECHNIC NORMAL UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] (1) Encoders and decoders require high-speed CPU processing, requiring more auxiliary memory and peripheral expansion circuits
[0004] (2) In the process of video encoding, most of the coefficients are discarded after image transformation, resulting in a serious waste of data and system resources
[0005] (3) In a multi-user environment, it is difficult for this technology to achieve optimal codec of source and channel
[0007] The main difference between the CS decoder and the traditional decoder is that the traditional decoding process is the inverse process of encoding, the decoder is relatively simple, and the encoder is more complex, while decoding based on compressed sensing theory is no longer the inverse process of encoding, but a process of seeking The process of solving underdetermined linear equations, compared with the encoder, the decoder is more complicated

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  • Video image compressed sensing coder-decoder system and coding-decoding method thereof

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Embodiment Construction

[0033] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0034] refer to Figure 1~3 , a video image compression sensing codec system according to an embodiment of the present invention mainly includes: a video acquisition subsystem for video acquisition, a processor module, an FPGA module, a memory module DDR, Flash, an Ethernet network port and a UART interface, Described video acquisition subsystem, FPGA module, memory module DDR and Flash are connected to processor module by communication respectively; Described processor module is respectively connected to end port and computer console through Ethernet network port, UART interface; Described processor The module includes an ARM core for system control and running operating system functions, and a DSP core for realizing voice and video codec functions using CS technology, and the DSP core and AR...

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Abstract

The invention relates to a video image compressed sensing coder-decoder system. The system comprises a video acquisition subsystem, a processor module and the like. An FPGA module, a memory module DDR, a Flash and the like are in communication connection with the processor module. The processor module is in communication connection with an opposite end port and a computer control console through an Ethernet port and a UART interface respectively. An ARM kernel and a DSP kernel are arranged in the processor module, wherein the ARM kernel is used for a processing system to control and operate an operating system function, and the DSP kernel achieves voice and video coding and decoding functions through the CS technology. The DSP kernel and the ARM kernels operate in an interactive processing mode. The coding and decoding method includes the steps that a first frame of a video sequence serves as a first key frame of a first group; threshold value judgment is carried out; judgment is repeatedly operated, and finally image processing and output are carried out. The problem about operating efficiency of a CPU is solved, hardware and software resources of a DSP video system are saved, and the complexity of system operation is reduced.

Description

technical field [0001] The invention belongs to the field of signal and information processing in communication, and in particular relates to a video image compression sensing codec system and a codec method thereof. Background technique [0002] The device of the existing video compression encoder is realized based on the traditional Shannon sampling theorem. Under the requirements of the theorem, the sampling rate of the signal must be greater than twice the bandwidth of the input signal in order to achieve accurate reconstruction of the signal. Therefore, in order to restore video images, in hardware, the codec needs powerful CPU processing functions, more peripheral memory configurations, and higher cost; in software, the number of image processing samples increases and the amount of data is huge. Therefore, the main problems of current video image codecs are: [0003] (1) Encoders and decoders require high-speed CPU processing, requiring more auxiliary memory and peri...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/42H04N19/423
CPCH04N19/42H04N19/423
Inventor 赵慧民戴青云魏文国任金昌容淳铭
Owner GUANGDONG POLYTECHNIC NORMAL UNIV