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Serializer/deserializer (SERDES) transmission verification method, node and system

A technology for transmitting verification and synchronizing frames, which is applied in transmission systems, digital transmission systems, single output arrangements, etc. It can solve problems such as non-affected, unstable SERDES, and board wiring that does not meet the requirements, so as to improve security, Guarantee SERDES access and enhance the effect of experience

Active Publication Date: 2017-01-11
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In systems that use SERDES for inter-board or inter-chip data communication, SERDES instability is often encountered. The reason for this phenomenon may be internal reasons such as SERDES reference clock instability. On the other hand, it may It is caused by external reasons such as the wiring on the board does not meet the requirements
In short, the data communication of SERDES is closely related to the external conditions required for SERDES work, including clock, reset, power supply voltage, magnetic field, electric field and other external conditions that may affect the stability of SERDES, and this effect is not completely predictable
[0003] How to ensure the stability of the SERDES channel and provide reliable data transmission, in related technologies, there is no effective solution to this problem

Method used

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  • Serializer/deserializer (SERDES) transmission verification method, node and system
  • Serializer/deserializer (SERDES) transmission verification method, node and system
  • Serializer/deserializer (SERDES) transmission verification method, node and system

Examples

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Embodiment 1

[0050] An embodiment of the present invention provides a SERDES transmission verification method. figure 1 It is a schematic flow chart of the transmission verification method of SERDES in the embodiment of the present invention; as figure 1 As shown, the method includes:

[0051] Step 101: The SERDES sending end sends a first synchronization frame to the SERDES receiving end.

[0052] Step 102: After receiving the first synchronization frame, the SERDES receiving end sends a second synchronization frame to the SERDES sending end.

[0053] Step 103: After receiving the second synchronization frame, the SERDES sending end sends a third synchronization frame to the SERDES receiving end, so that the SERDES sending end and the SERDES receiving end respectively determine their own transmission paths and The receiving paths are all in normal state.

[0054] In this embodiment, the SERDES sending end and the SERDES receiving end are respectively two ends of the SERDES path. Where...

Embodiment 2

[0062] Based on the SERDES transmission verification method provided in Embodiment 1, in this embodiment, the frame headers of the first synchronization frame, the second synchronization frame, and the third synchronization frame are all provided with a first identification bit and a second identification bit; when the first identification bit is at a preset value, it indicates that the receiving channel at the local end is in a normal state; when the second identification bit is at a preset value, it indicates that the receiving channel at the opposite end is in a normal state.

[0063] In this embodiment, the first synchronization frame, the second synchronization frame, and the third synchronization frame may all be referred to as synchronization frames. In this embodiment, data frames are also transmitted between the SERDES sending end and the SERDES receiving end in addition to synchronous frames; the synchronous frames and the data frames may be called private frames in t...

Embodiment 3

[0089] The embodiment of the present invention also provides a SERDES transmission verification method, and the SERDES transmission verification method described in this embodiment is applied to the sending end. The methods include:

[0090] Step 401: The SERDES sending end sends a first synchronization frame to the SERDES receiving end, and after receiving the second synchronization frame sent by the SERDES receiving end, the SERDES sending end determines that both its sending path and receiving path are in a normal state.

[0091] Step 402: The SERDES sending end sends a third synchronization frame to the SERDES receiving end.

[0092] Wherein, the frame headers of the first synchronization frame, the second synchronization frame and the third synchronization frame are all provided with a first identification bit and a second identification bit; when the first identification bit is at a preset value It indicates that the receiving channel at the local end is in a normal sta...

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Abstract

The embodiment of the present invention discloses an SERDES transmission verification method, node and system, wherein the method comprises the steps of using an SERDES sending terminal to send a first synchronization frame to an SERDES reception terminal; after the SERDES reception terminal receives the first synchronization frame, using the SERDES reception terminal to send a second synchronization frame to the SERDES sending terminal; after the SERDES sending terminal receives the second synchronization frame, using the SERDES sending terminal to send a third synchronization frame to the SERDES reception terminal, so that the SERDES sending terminal and the SERDES reception terminal can separately determine that the respective sending and reception accesses are both located in the normal states.

Description

technical field [0001] The invention relates to data communication interface technology, in particular to a SERDES transmission verification method, node and system. Background technique [0002] Because SERDES has the characteristics of high speed and high precision, less pins, and low power consumption, it is widely used in modern communication chips. In systems that use SERDES for inter-board or inter-chip data communication, SERDES instability is often encountered. The reason for this phenomenon may be internal reasons such as SERDES reference clock instability. On the other hand, it may It is caused by external reasons such as the wiring on the board does not meet the requirements. In short, the data communication of SERDES is closely related to the external conditions required for SERDES work, including clock, reset, power supply voltage, magnetic field, electric field and other external conditions that may affect the stability of SERDES, and this effect is not comple...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B17/30
CPCH04B17/30H04L1/00H04L7/10H04L12/40H04L12/40045H03K5/13H03M9/00H03M13/09H04J3/0658
Inventor 刘新良
Owner SANECHIPS TECH CO LTD
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