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Input buffer for high-speed time-interleaved analog-digital converter

A technology of input buffer and analog-to-digital converter, applied in the direction of analog-to-digital converter, analog-to-digital conversion, code conversion, etc., can solve the problems of input signal influence, etc., and achieve the goal of increased bandwidth, high linearity, and reduced power consumption Effect

Active Publication Date: 2017-01-25
FUDAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Due to the impact of the above charge injection and signal rebound, the high-precision switch will have a greater impact on the input signal during the on-off process

Method used

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  • Input buffer for high-speed time-interleaved analog-digital converter
  • Input buffer for high-speed time-interleaved analog-digital converter
  • Input buffer for high-speed time-interleaved analog-digital converter

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Embodiment Construction

[0027] An input buffer applied to a high-speed time-interleaved analog-to-digital converter proposed in the present invention will be described below with reference to the accompanying drawings. It is worth noting that the input buffer provided by the present invention can have many different indicators and performance implementation methods, and the two-stage source follower input buffer in the present invention can also have various application scenarios. The implementation below only provides a typical implementation circuit of the present invention, which is only used to illustrate the formation and use of the present invention, and is not intended to limit the present invention.

[0028] The implementation target of the input buffer provided by the present invention is to be applied to an ADC with a sampling rate of 3GS / s and a precision of 12 bits. The single channel of this ADC is 750MS / s, 12 precision. Therefore, the ADC adopts a four-channel time-interleaved structur...

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Abstract

The invention belongs to the technical field of the integrated circuit, and relates to an input buffer for a high-speed time-interleaved analog-digital converter. The input buffer comprises a time-interleaved analog-digital converter model, a stage of buffer of low-level to high-level, and a stage of buffer of high-level to low-level. Two stages of the buffers use the structure of source follower, the input signal and each channel are insulated by the first stage of the buffer, and the signal interference between the channels and the effect caused by the charge injection to the prior stage of the signal are reduced by the second stage of the buffer in each channel. The input buffer is used for the time-interleaved high-speed high-precision Nyquist ADC, a feedforward capacitance is introduced into the first stage of the buffer for improving the precision, and two routes of N and P input are introduced into the second stage of the buffer for improving the speed and reducing the power consumption. Compared with the current buffer, the input buffer uses two stages of the buffer structures suitable for the time-interleaved ADC, and the optimization design solution is provided for each stage design.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an input buffer used in a time-interleaved analog-to-digital converter. Background technique [0002] High-performance digital-analog hybrid integrated circuit is the key technology of the new generation ultra-wideband wireless communication system. Among them, the analog-to-digital converter (ADC) is an essential core device in the communication physical layer. Its bandwidth, speed, accuracy, cost, power consumption and reliability determine the performance and function of wireless base stations and terminals to some extent. [0003] When a single ADC of a certain structure has reached the limit of the existing design conditions and process conditions, parallelization is an effective and even the only way to break through the restriction of the conversion rate. Each sub-channel ADC (Sub-ADC) alternately samples the input, while maintaining high precisio...

Claims

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Application Information

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IPC IPC(8): H03M1/12H03M1/08
CPCH03M1/0845H03M1/121H03M1/1245
Inventor 任俊彦陈勇臻王晶晶吴奕旻倪哲侃叶凡李宁
Owner FUDAN UNIV