NAND memory structure, NAND memory structure formation method and three dimensional memory array

Abstract

The invention discloses an NAND memory structure formation method. The formation method comprises the following steps of providing a semiconductor substrate, and forming multiple groups of source electrode selection transistors in the substrate; forming a storage unit of a vertical laminated structure on the source electrode selection transistors, wherein the storage unit of the vertical laminated structure comprises a vertical channel, a multi-layer storage gate medium, and a bit line selection tube grid and a laminated word line formed outside the vertical channel, and drain electrodes of the source electrode selection transistors are contacted with the multi-layer storage gate medium on the bottom of the vertical channel; and forming a bit line on the storage unit of the vertical laminated structure; and applying breakdown voltage to the multi-layer storage gate medium between the drain electrodes of the source electrode selection transistors and the vertical channel through the bit line and the laminated word line. The NAND memory structure formation method can reduce the process difficulty and the cost and improve the integration density. The invention also discloses an NAND memory structure and a formation method thereof and a three dimensional memory array.

Description

technical field [0001] The invention belongs to the technical field of information storage, and in particular relates to a method for forming a NAND memory, a structure of the NAND memory and a method for forming the same, and a three-dimensional NAND memory array. Background technique [0002] NAND memory technology continues to develop, its storage performance continues to improve, and many related technologies continue to propose new structural solutions. [0003] Among them, BiCS (Bit Cost Scalable) technology is "planar gate vertical channel" and "gate first, then channel" technology, refer to relevant literature, for example, [1], H.Tanaka et al., Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory, 2007Symposium on VLSI Technology Digest of Technical Papers, pp.14-15. [2], US7,852,675: Threedimensional stacked nonvolatile semiconductor memory, this patent describes the structural method of BICS vertical arrangement. Specifical...

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Problems solved by technology

The "gate replacement" process adds multiple dielectric deposition and etching process steps, and the process complexity is very high

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