A power-on reset circuit

Abstract

The invention discloses a power-on reset circuit, comprising a sampling delaying circuit which is used for carrying out sampling and delayed output on a power supply voltage; a hysteresis circuit which is used for carrying out short circuit on part of the sampling resistance under the normal working condition after a reset signal is generated, thereby carrying out a hysteresis effect on a change of the power supply voltage; a discharge circuit which is connected with the sampling delaying circuit, thereby enabling charges on a capacitor of the sampling delaying circuit to flow out rapidly when a power supply is powered off; a reset signal generation circuit which is used for rising along with the power supply voltage in the initial establishment stage of the power supply voltage and overturning after the power supply voltage reaches certain amplitude, thereby outputting an inverted signal; and a buffer circuit which is used for buffering the signal output by the reset signal generation circuit, thereby reducing the influence on the reset signal generation circuit and improving load carrying capacities of the reset signal and the inverted reset signal. Through application of the circuit, Vtrigger is enabled to have a stable window; and moreover, a RESET positive pulse can be output under the condition that the power supply is powered off and powered on in a short time.

Description

technical field [0001] The invention relates to the technical field of analog integrated circuits, in particular to a power-on reset circuit with a discharge structure. Background technique [0002] figure 1 It is a circuit structure diagram of a power-on reset circuit in the prior art. like figure 1 As shown, the power-on reset circuit includes: a sampling delay circuit 10 , a hysteresis circuit 20 , a reset signal generation circuit 40 and a buffer circuit 50 . [0003] Wherein, the delay circuit 10 is used to divide the voltage of the power supply VDD by means of series resistors (R1 / R2 / R3) to generate a voltage V0 to control the switching of the NMOS transistor N0 of the reset signal generating circuit 40 . When VDD is low (such as VDD is lower than the flip point Vtrigger of POR (power-on reset), the resistance of NMOS transistor N0 is much larger than R0, the voltage of V2 node follows VDD, and the RESET voltage also follows VDD; when VDD is high (VDD high Vtrigger...

AI Technical Summary

Problems solved by technology

[0008] 2. When the power is turned off and on again, the charge on the capacitor C0 cannot be quickly discharged through the resistors R1, R2, and R3

When the power is cut off and powered on for a short time, V0 maintains a high voltage, and the NMOS transistor N0 is always on, and POR (power-on reset) cannot output RESET positive pulses.

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