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Redundant fault-tolerant technology applied to FPGA (Field Programmable Gate Array) digital circuit

A digital circuit, redundant fault-tolerant technology, applied in the field of redundant fault-tolerant technology, can solve problems such as system failure and wrong data information, and achieve the effects of reducing hardware scale, improving reliability, and improving operating efficiency

Inactive Publication Date: 2017-03-22
汪鹏
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  • Abstract
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Problems solved by technology

[0006] If one bit of the configuration data changes, that is, from "0" state to "1" state, or from "1" state to "0" state, then the corresponding circuit will change the original behavior and implement non-user settings The operation, this effect will eventually be transmitted to the output of the device, causing the user to get unexpected results, or get wrong data information, causing the system to fail

Method used

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  • Redundant fault-tolerant technology applied to FPGA (Field Programmable Gate Array) digital circuit
  • Redundant fault-tolerant technology applied to FPGA (Field Programmable Gate Array) digital circuit
  • Redundant fault-tolerant technology applied to FPGA (Field Programmable Gate Array) digital circuit

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Embodiment Construction

[0014] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0015] figure 1 Shown is the structure of the bottom layer of SRAM FPGA. The leftmost dashed box in the figure is the CLB programmable logic block. For Virtex-5 series FPGAs, each CLB consists of two Slices, and each Slice contains 4 LUTs and 4 flip-flops. According to the user's design, the CLB can be configured as the corresponding combinatorial logic or sequential logic, and it can also be configured as distributed RAM or distributed ROM for use. The LUT in the CLB is mainly used to realize the combinatorial logic, and the trigger is mainly used for It is used to realize the intermediate results of sequential logic and storage circuit operation. BRAM is an on-chip storage resource used to implement various storage functions and improve the overall operating efficiency of the FPGA. M is a configuration memory unit, which is used to store configuration data of th...

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Abstract

The invention discloses a redundant fault-tolerant technology applied to an FPGA (Field Programmable Gate Array) digital circuit. The concept of a digital circuit reconfigurable technology is applied to fault tolerance of an FPGA logical resource circuit fault so as to improve the reliability of system operation. Switching of a logical function for a digital circuit reconfigurable region A is realized through dynamic loading of a circuit bit stream data configuration file A1.bit or A2.bit.

Description

technical field [0001] The invention relates to a redundant fault-tolerant technology applied to FPGA digital circuits, which can effectively reduce the influence of short channel effect, and is especially suitable for the dynamic reconfigurable technology of logic circuit part of FPGA digital circuits. Background technique [0002] Because there are a large number of complex high-energy particles in the space environment, they run randomly and randomly, and it is inevitable that they will collide with semiconductor devices in aerospace equipment. When these high-energy particles hit sensitive areas in the device, they can easily cause short-channel effects, which can change the function of the device. The logic resource configuration storage unit in the SRAM FPGA is very sensitive to the short channel effect, and the configuration bit stream information is prone to change. The content in the FPGA configuration memory determines the top-level circuit structure of the FPGA, w...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07
Inventor 汪鹏
Owner 汪鹏
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