Structures and methods for interconnection
A technology for electrical connection, etching stop layer, applied in the field of structures and methods for interconnection, and can solve problems such as damage to conductive features, misalignment, etc.
Active Publication Date: 2020-07-31
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
However, as semiconductor technology moves forward to advanced technology nodes with smaller feature sizes, such as 20nm, 16nm, or below, various issues with smaller tolerances can arise, such as misalignment, damage to already formed conductive features, etc. damage etc.
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[0008] It should be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. Furthermore, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, the formation of a first feature on a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed interposed between the first feature and the second feature. An embodiment of the second feature such that the f...
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Abstract
The present invention relates to structures and methods for interconnection. A method according to an embodiment of the invention includes: providing a substrate having a first conductive feature in a first layer of dielectric material; forming a first etch stop layer on the first layer of dielectric material, wherein the first etch stop forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming on the second dielectric material layer a patterned mask layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby forming a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a first etch stop in the second trench Two conductive features.
Description
technical field Background technique [0001] In semiconductor technology, photolithographic processes may be used to define integrated circuit patterns on a substrate. A multilayer copper interconnect comprising vertical interconnect vias / contacts and horizontal interconnect metal lines is formed using a damascene or dual damascene process. During the damascene process, the vias (or contacts) are filled with a plug fill material, and then the material is polished back. However, as semiconductor technology moves forward to advanced technology nodes with smaller feature sizes, such as 20nm, 16nm, or below, various issues with smaller tolerances can arise, such as misalignment, damage to already formed conductive features, etc. damage etc. [0002] Therefore, the present invention provides an interconnection structure and its manufacturing method to solve the above problems. Contents of the invention Description of drawings [0003] Aspects of the present invention are be...
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IPC IPC(8): H01L21/768H01L23/535
CPCH01L21/76801H01L21/76838H01L23/535H01L23/53223H01L23/53238H01L23/53266H01L23/53295H01L21/76802H01L21/76811H01L21/76832H01L23/5226H01L21/02019H01L21/02118H01L21/02225H01L21/306H01L21/30604H01L21/31055H01L21/31133H01L21/31144H01L21/3212H01L21/76805H01L21/7684H01L21/76877H01L23/528H01L23/5329
Inventor 黄建桦蔡政勋李忠儒蔡承孝
Owner TAIWAN SEMICON MFG CO LTD