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pldmos device and its manufacturing method

A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of low doping concentration, device source-drain punch-through, etc., and achieve the effect of suppressing source-drain punch-through

Active Publication Date: 2019-06-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] because figure 1 In the existing structure shown, since the channel region is directly composed of the N-type epitaxial layer 103, and because the doping concentration of the N-type epitaxial layer 103 is relatively light, when the channel length of the channel region is short, such as less than 2.5 μm The device suffers from source-drain punchthrough

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  • pldmos device and its manufacturing method
  • pldmos device and its manufacturing method
  • pldmos device and its manufacturing method

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Embodiment Construction

[0062] like figure 2 Shown is the structural diagram of the PLDMOS device of the embodiment of the present invention, the PLDMOS device of the embodiment of the present invention includes:

[0063] N-type epitaxial layer 103a, the N-type epitaxial layer 103a is formed on the surface of a P-type substrate such as a P-type silicon substrate 101, and an N-type epitaxial layer 103a is isolated from the P-type substrate 101. buried layer 102 .

[0064] A P well 105 is formed in a selected region of the N-type epitaxial layer 103a, and the P well 105 serves as a drift region.

[0065] There is a field oxide layer on the surface of the N-type epitaxial layer 103a in the region of the P well 105, and this field oxide layer is called the first field oxide layer 104a.

[0066] The channel region is formed by superimposing N-type ion-implanted impurities on the N-type epitaxial layer 103a, and the N-type doping concentration of the channel region is increased through the N-type ion-im...

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Abstract

The invention disclosers a PLDMOS device comprising a N-type epitaxial layer, a P trap, a gate medium layer, a polysilicon gate, a source zone and a drain zone; a channel region is formed by stacking the N-type epitaxial layer with N type ion injection impurity; the N type ion injection impurity can improve N-type doping concentration of the channel region, thus preventing source-drain penetration; P-type ion injection impurity is formed on the surface of the channel region; the P-type ion injection impurity can cancel off the influences on the channel region surface by the N type ion injection impurity, thus allowing the device threshold voltage to return to the initial threshold voltage decided by the body doping concentration of the N-type epitaxial layer. The invention also discloses a PLDMOS device making method. The device and method can prevent device source-drain penetration without affecting the device threshold voltage, so the device can be adapted to smaller channel length.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a PLDMOS device, that is, a P-type LDMOS device; the invention also relates to a method for manufacturing the PLDMOS device. Background technique [0002] LDMOS is currently widely used in power management circuits due to its advantages of high voltage resistance, high current drive capability, extremely low power consumption, and integration with CMOS. like figure 1 Shown is a structural diagram of an existing PLDMOS device, and the existing PLDMOS device includes: [0003] N-type epitaxial layer 103, the N-type epitaxial layer 103 is formed on the surface of a P-type substrate such as a P-type silicon substrate 101, and an N-type epitaxial layer 103 is isolated from the P-type substrate 101. buried layer 102 . [0004] A P well 105 is formed in a selected region of the N-type epitaxial layer 103, and the P well 105 serves as a drift region. [...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66681H01L29/7816
Inventor 段文婷
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP