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A kind of semiconductor device and its manufacturing method, electronic device

A manufacturing method and semiconductor technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of poor off-state characteristics of MOSFET devices, short channel effects, lower leakage-induced barriers, and increased static power consumption etc. to achieve the effect of reducing the degradation of carrier mobility, reducing the channel electric field, and reducing the leakage current

Active Publication Date: 2019-12-10
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, as the channel size continues to decrease, the short channel effect and the drain-induced barrier lowering (DIBL) effect are becoming more and more serious, resulting in poor device performance.
At the same time, the leakage-induced barrier lowering (DIBL) effect will affect the sub-threshold characteristics, such as degrading the sub-threshold swing (or S factor). In the scaling rules of large-scale digital integrated circuits, the constant voltage scaling rule , the constant electric field reduction rule, etc. cannot reduce the S value, and the leakage current in the subthreshold region deteriorates the off-state characteristics of the MOSFET device and increases the static power consumption

Method used

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  • A kind of semiconductor device and its manufacturing method, electronic device
  • A kind of semiconductor device and its manufacturing method, electronic device
  • A kind of semiconductor device and its manufacturing method, electronic device

Examples

Experimental program
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Effect test

Embodiment 1

[0052] Figure 2a-Figure 2o A cross-sectional view of a device obtained in various steps in the process flow for manufacturing a semiconductor device according to an embodiment of the present invention. The following will refer to and Figure 2a-Figure 2o The manufacturing method of the semiconductor device of the present invention is described in detail.

[0053] First, if Figure 2a As shown, a semiconductor substrate 200 is provided, an insulating layer 201 and a patterned mask layer 202 are formed on the semiconductor substrate 200, and the semiconductor substrate 200 is etched using the patterned mask layer 202 as a mask, to form trenches 203 .

[0054] The semiconductor substrate 200 may be at least one of the materials mentioned below: silicon, germanium. In addition, other devices, such as PMOS and NMOS transistors, may be formed on the semiconductor substrate. An isolation structure may be formed in the semiconductor substrate, and the isolation structure is a sh...

Embodiment 2

[0082] The present invention also provides a semiconductor device 300 manufactured by the method described in Embodiment 1, including: a semiconductor substrate 200, an insulating layer 201 having a trench 203 is formed on the semiconductor substrate 200, and an insulating layer 201 is formed in the trench 203 region. The channel region 205, the gate oxide layer 207 and the gate 215, and the source 218A and drain 218B located on both sides of the gate 215; wherein, the surface layer of the semiconductor substrate 200 corresponding to the bottom of the trench 203 forms a heavily doped region 204 ; the source 218A and the drain 218B form Schottky contacts with the channel region 205 .

[0083] Preferably, the source 218A and the drain 218B are metal silicides, such as PtSi or ErSi 2。

[0084] Preferably, the channel region 205 is an undoped layer or a lightly doped layer.

[0085] Preferably, the heavily doped region 204 is a P-type heavily doped region.

[0086] In addition,...

Embodiment 3

[0090] The present invention further provides an electronic device including the aforementioned semiconductor device. Figure 4 It is a schematic structural diagram of an electronic device according to an embodiment of the present invention. Due to the inclusion of the aforementioned semiconductor device, the self-heating effect, leakage-induced barrier lowering effect and sub-threshold characteristics of the device can be improved, and the electronic device also has the above-mentioned advantages.

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Abstract

The present invention provides a manufacturing method of a semiconductor device. The method includes the following steps that: step a, a semiconductor substrate is provided, an insulating layer with a groove and a mask layer are formed on the semiconductor substrate; step b, a heavily-doped region is formed on the surface layer of the semiconductor substrate, wherein the surface layer of the semiconductor substrate is adjacent to the bottom of the groove; step c, a channel region, a gate oxide layer and a gate are formed in the groove; and step d, the mask layer is removed, a raised source region and a raised drain region are formed on the insulating layer at two sides of the gate, wherein the source region and the raised drain region are in Schottky contact with the channel region. With the manufacturing method of the semiconductor device of the invention, the self heating effect, leakage-induced barrier reduction effect and sub-threshold characteristic of the device can be improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] In the contemporary information society, driven by the dual drive of chip integration density maximization and circuit performance optimization, the core MOSFET devices of integrated circuits are continuously scaled down. Since the 1970s, due to the development of ion implantation technology, MOSFETs with extremely small sizes have been manufactured, and the theory of MOSFET scaling down has been established at the same time. With the continuous reduction of the size of MOSFET devices, various small size effects are gradually revealed. For example, as the channel size continues to decrease, the short channel effect and the drain-induced barrier lowering (DIBL) effect become more and more serious, resulting in poor device performance. At the same time, t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
Inventor 刘金华
Owner SEMICON MFG INT (SHANGHAI) CORP