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Methods and apparatus for ldmos devices with cascaded resurf implants and double buffers

An ion implantation, a part of the technology, used in semiconductor devices, electrical solid state devices, semiconductor/solid state device manufacturing, etc., can solve problems such as increasing production costs and adding complexity to manufacturing processes

Active Publication Date: 2020-06-05
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Likewise, the use of buried layers "NBL" and "PBL" adds complexity to standard CMOS semiconductor fabrication processes by requiring additional and specific photomask, patterning and implantation steps, thereby increasing production costs

Method used

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  • Methods and apparatus for ldmos devices with cascaded resurf implants and double buffers
  • Methods and apparatus for ldmos devices with cascaded resurf implants and double buffers
  • Methods and apparatus for ldmos devices with cascaded resurf implants and double buffers

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Experimental program
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Embodiment Construction

[0015] The figures are not necessarily drawn to scale.

[0016] There is a continuing need for LDMOS transistor devices with improved reduced surface field effect performance. There is a need for LDMOS transistors that can be fabricated with standard CMOS devices with reduced process steps and reduced cost when compared to existing methods. There is a need for LDMOS devices that have very high breakdown voltage BVdss, reduced on-resistance, improved CHC performance, and require silicon area lower than that required by existing LDMOS devices at a lower cost.

[0017] Arrangements forming various aspects of the present application provide an LDMOS device formed in a semiconductor process having a double buffer arrangement and further formed using a chained ion implantation step to create an LDMOS device in both the drift region and the D-well region Contains cascaded resurf diffusers for high performance. A corresponding method arrangement is also disclosed.

[0018] In an ex...

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PUM

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Abstract

In the depicted example, an LDMOS device (1200) includes: at least one drift region (1222) disposed in a portion of a semiconductor substrate (1210); at least one isolation structure (1252) located in the semiconductor substrate at the surface of the bottom (1210); a D-well region positioned adjacent to a portion of the at least one drift region (1222), and the intersection of the drift region (1222) and the D-well region forms a first conductivity A junction (1226) between a type and a second conductivity type; a gate structure (1282), which is disposed over the semiconductor substrate (1210); a source contact region (S), which is disposed on the D on the surface of the well region; a drain contact region (D) disposed adjacent to the isolation structure (1252); and a double buffer region comprising: a first buried layer (1228) located on the D-well region and said drift region (1222) below and doped to said second conductivity type; and a second high voltage deep diffusion layer (1218) located on said first buried layer (1228) and is doped to the first conductivity type.

Description

technical field [0001] This relates to the field of integrated circuits (ICs), and more specifically the fabrication of lateral double diffused metal oxide semiconductor (LDMOS) devices. Background technique [0002] The need for transistors that can provide high power drive capabilities on semiconductor integrated circuits has led to the development of lateral double diffused metal oxide semiconductor (LDMOS) devices. Applications of particular interest for LDMOS devices include high-side and low-side drivers for output buffers and radio frequency (RF) circuits. Double diffused MOS devices (DMOS) are used in applications where high voltage capability and low resistance are required. LDMOS transistors exhibit high breakdown voltage BVdss and low on-resistance RDSon, and are therefore well suited for high power applications. [0003] In transistors formed in DMOS processes, the source and back gate diffusions are formed by simultaneous or simultaneous ion implantation into ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/80
CPCH01L21/823814H01L27/0922H01L29/66659H01L29/66689H01L21/761H01L21/76224H01L29/7816H01L29/7835H01L29/0847H01L29/0878H01L29/1041H01L29/1083H01L29/1087H01L29/1095H01L29/0634H01L21/26513H01L29/0653H01L29/7823H01L29/0649H01L29/0856H01L29/0873H01L29/66681H01L29/78
Inventor 蔡军
Owner TEXAS INSTR INC