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Static timing analysis method and device

A static timing analysis and timing technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as low efficiency, and achieve the effect of improving efficiency and improving efficiency

Inactive Publication Date: 2017-05-17
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problem of inefficiency caused by modifying the design when performing static timing analysis in the prior art

Method used

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  • Static timing analysis method and device

Examples

Experimental program
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Embodiment 1

[0054] This embodiment provides a static timing analysis method, please refer to figure 1 , including:

[0055] S101. Establish a corresponding sequence diagram according to the current netlist;

[0056] S102. When the netlist changes, record the instance in the changed netlist and the type of the change;

[0057] S103. Update the sequence diagram according to the changed instance and the type of change;

[0058] S104. Perform static timing analysis according to the updated timing diagram to obtain a static timing analysis result.

[0059] In the design of digital integrated circuits, the static timing analysis of the circuit is often essential. The static timing analysis can verify whether the circuit design meets the designer's constraints according to the delay of the internal logic and wiring of the circuit. The advantage of static timing analysis is that it can exhaust all paths without inputting test vectors, can conduct a comprehensive timing function check on the ci...

Embodiment 2

[0108] This embodiment provides a static timing analysis device, please refer to Figure 6 , including:

[0109] The creating module 601 is used to create a corresponding sequence diagram according to the current netlist;

[0110] A recording module 602, configured to record instances in the changed netlist and the types of changes thereof when the netlist changes;

[0111] An updating module 603, configured to update the timing diagram according to the changed instance and the type of the change;

[0112] The analysis module 604 is configured to perform static timing analysis according to the updated timing diagram, and obtain a static timing analysis result.

[0113] In the design of digital integrated circuits, the static timing analysis of the circuit is often essential. The static timing analysis can verify whether the circuit design meets the designer's constraints according to the delay of the internal logic and wiring of the circuit. The advantage of static timing ana...

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Abstract

The embodiment of the invention provides a static timing analysis method and device. A corresponding time sequence diagram is created according to a current network table, when the network table changes, examples changing in the network table and the types of the changes are recorded, the time sequence diagram is updated according to the changing examples and the types of the changes, static timing analysis is conducted according to the updated time sequence diagram, and a static timing analysis result is obtained. By means of the method and device, the time sequence diagram does not need to be created again when the network table changes, so time sequence diagram creation efficiency is improved, and static timing analysis efficiency is further improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a static timing analysis method and device. Background technique [0002] The design of digital integrated circuits must meet a certain timing relationship, otherwise the circuit design will not be able to achieve the desired effect. The main function of timing analysis is to verify whether the designer's constraints are met according to the delay of the internal logic and wiring of the circuit. Timing analysis is divided into dynamic timing analysis and static timing analysis. Dynamic timing analysis, that is, simulation, dynamic timing analysis test vector scale is huge and may be incomplete, and finally consumes a lot of development resources and cannot expose all timing problems. The advantage of static timing analysis is that it can exhaust all paths without inputting test vectors, can conduct a comprehensive timing function check on circuit design, and can also us...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 陶思敏张恒
Owner SHENZHEN PANGO MICROSYST CO LTD
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