Method for reducing adjacent channel power ratio based on CIC filter and CIC filter

Abstract

The invention discloses a method for reducing an adjacent channel power ratio based on a CIC filter and the CIC filter. The method comprises the steps of inputting a data signal into the CIC filter, wherein a comb filter of the CIC filter outputs data; generating an integral pulse cic_inter_fs and interpolating the data signal through an interpolation module; controlling the comb filter to output switching of data and ''0'' interpolation by combined logic, if the cic_inter_fs is equal to '0 ', interpolating ''0'' value, and inputting full 0 data by an integrator; if the cic_inter_fs is equal to '1 ', inputting the output data of the comb filter by the integrator; and if the ''0'' value is interpolated, calculating data bit width through a bit width control packet module, and outputting the data by the integrator. According to the method for reducing the adjacent channel power ratio based on the CIC filter and the CIC filter provided by the invention, a CIC algorithm is realized through logic, so the adjacent channel power ratio (ACPR) of a reader reaches a protocol standard, and the reading efficiency of an external filed application of the reader is not reduced.

Description

technical field [0001] The invention belongs to the field of multi-rate conversion of digital signal processing, and in particular relates to a method for reducing adjacent channel power ratio based on a CIC filter and a CIC filter. Background technique [0002] In the part of digital baseband processing, it is usually necessary to perform digital up-conversion or down-conversion processing on the signal. The CIC filter is a low-pass rate change filter, which is composed of an integrator (integrator) and a comb (Comb) filter stage. Depending on the position of the integrator and the comb, the functions of Decimation and Interpolation can be realized respectively. In the extraction type CIC, the integrator is in the front, followed by the comb, which realizes down-conversion processing. The insertion type CIC is the opposite, the comb is in the front, and the integrator is in the back, which realizes up-conversion processing. [0003] Before the digital baseband signal is s...

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Problems solved by technology

[0004] FPGA implementation of CIC filter will cause the following problems: CIC filter will cause high data overflow problem due to integrator, the bit width of the original data needs to be extended; the stop band attenuation and transition band of CIC filter are not very good, generally through CIC The cascade of the filter can be improved, but the cascade order of the CIC filter will make the overflow problem more serious, which requires more extension bits, resulting in a vicious circle

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