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Three-dimensional storage and formation method therefor

A memory, three-dimensional technology, which is applied in the manufacture of electric solid-state devices, semiconductor devices, and semiconductor/solid-state devices, etc., can solve the problems of reducing chip space utilization, large size, and complicated manufacturing process of flash memory storage units, and improve space utilization. , the effect of simplifying the process and reducing the volume

Active Publication Date: 2017-06-20
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the manufacturing process of the existing three-dimensional NAND gate flash storage unit is complicated and the volume is large, which will reduce the space utilization of the chip

Method used

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  • Three-dimensional storage and formation method therefor

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Embodiment Construction

[0028] As mentioned in the background art, the manufacturing process of the existing three-dimensional NAND flash storage unit is complicated and the volume is large, which will reduce the space utilization rate of the chip.

[0029] Combining with a three-dimensional NAND gate flash storage unit, the reason why the manufacturing process of the three-dimensional NAND flash storage unit is complicated and the volume is large is analyzed.

[0030] Please refer to figure 1 , figure 1 It is a structural schematic diagram of an existing three-dimensional NAND gate flash storage unit, including: a substrate 100; an isolation layer 103 located on the surface of the substrate 100; a bottom selection gate 104 located on the surface of the isolation layer 103; Several layers of overlapping control gates 107 on the gate 104; a top selection gate 109 located on the control gate 107; The source line doped region 120 in the bottom; the channel via hole (not marked) passing through the top...

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PUM

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Abstract

The invention discloses a three-dimensional storage and a formation method therefor. The three-dimensional storage comprises a substrate, a plurality of separated stacking layer structures, an isolation layer, a connecting structure and a plurality of inserting plugs, wherein the substrate comprises a device region and a connecting region which are arranged adjacently; the multiple separated stacking layer structures are positioned on the device region and the connecting region of the substrate; the stacking layer structures comprise multiple layers of stacked grids; the isolation layer is positioned on the device region, between adjacent stacking structures, of the substrate; the connecting structure is positioned on the connecting region of the substrate; the connecting structure is connected with the adjacent stacking structures; the connecting structure comprises multiple layers of stacked electric connecting layers; the two ends of each electric connecting layer are connected with the grids on the same layer in the adjacent stacking structures; the multiple inserting plugs are positioned on the surfaces of the grids in each layer; and each inserting plug is electrically connected with the grids in contact, the grids on the same layer with the grids in contact, and the electric connecting layers on the same layer with the grids in contact. By virtue of the formation method, the number of the inserting plugs can be reduced, the process can be simplified, the size of the storage can be reduced, and the space utilization rate of the chip can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof. Background technique [0002] In recent years, the development of flash memory (flash memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density of the flash memory while reducing the bit cost, a three-dimensional NAND (3D NAND) flash memory is proposed. [0003] A three-dimensional NAND (3D NAND) flash memory has a plurality of gate layers stacked on a substrate, and a vertical channel runs through the plurality of gate layers. The bottom gate layer is used as a bottom selection transistor, multiple middle gate layers are used as storage transistors, and the top g...

Claims

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Application Information

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IPC IPC(8): H01L27/115H01L21/77
CPCH01L21/77H10B69/00H10B43/10H10B43/50H10B43/40H10B43/35H10B43/27H10B41/27H10B41/50H10B41/10H10B43/30H01L21/02164H01L21/02271H01L21/0262H01L21/28568H01L21/31053H01L21/31111H01L21/31144H01L21/76802H01L21/76877H01L21/76895H01L23/5226H01L23/528H01L23/53214H01L23/53228H01L23/53257H01L29/0847H01L29/1037
Inventor 徐强刘藩东霍宗亮夏志良杨要华洪培真华文宇何佳
Owner YANGTZE MEMORY TECH CO LTD
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