System-level error correction SAR analog-digital converter

Abstract

The invention provides a system-level error correction SAR analog-digital converter comprising a bootstrapped sampling switch, a first capacitor array, a second capacitor array, a switch array, a comparator, a successive approximation register asynchronous logic module and an error correction comparator used for adjusting the working mode according to the change of an input differential signal. According to the system-level error correction SAR analog-digital converter provided by the invention, the comparator switches between two working modes, and the comparator can work in different working states according to the difference of the amplitudes of the input signals of the comparator, thereby optimizing the working mode of the comparator, improving the working efficiency of the comparator and further improving the performance of the whole SARADC. Moreover, the system-level error correction SAR analog-digital converter provided by the invention does not need to import an additional redundant bit to perform error correction, thereby simplifying the design difficulty and improving the working speed of the whole SARADC.

Description

Technical field [0001] The invention relates to the field of integrated circuits, in particular to a system-level error correction SAR analog-digital converter. Background technique [0002] The successive approximation register analog-to-digital converter (hereinafter referred to as SARADC) is a common structure for medium to high-resolution applications with a sampling rate of less than 5Msps (million samples per second). The resolution of SAR ADC is generally 8 to 16 bits, and it has the advantages of low power consumption, simple structure, small layout area and low cost. These features make this type of ADC have a wide range of applications, such as portable / battery-powered meters, pen input quantizers, industrial control, and data / signal acquisition. In recent years, with the continuous expansion of mobile terminals and integrated analog front-end applications, the demand for low-power, medium- and high-speed ADCs is increasing. With the continuous progress of integrated ...

AI Technical Summary

Problems solved by technology

However, for different input signals, the working state of the comparator is fixed, which makes it impossible for the comparator to adjust its working mode in time according to the change of the input signal. On the other hand, if a redundant bit is used to compare the high bit The result is corrected, and then enters the low-order successive approximation process, but due to the addition of redundant bits, it will cause an increase of a comparison cycle, which reduces the working speed of the entire ADC

Images